Analysis of modeling styles on Network-on-Chip simulation

Abstract

This paper analyses the effects of Network-on-Chip (NoC) models written in SystemC on simulation speed. Two Register Transfer Level (RTL) models and Approximately Timed (AT) and Loosely Timed (LT) Transaction Level (TL) models are compared against reference RTL VHDL 2D mesh model. Three different mesh sizes are evaluated using a commercial simulator and OSCI SystemC reference kernel. Studied AT model achieved 13–40x speedup with modest 10% estimation error.