Multiple node upset mitigation in TPDICE-based pipeline memory structures

Abstract

Traditional single disruption tolerant radiation hardened SRAM designs are vulnerable to failure when exposed to particle strikes that induce multiple node disruptions. Such events become likely when devices with small feature sizes are operated in highly radioactive environments. This paper analyzes the effectiveness of hardened by design techniques created with the intent to mitigate multiple node disruptions in 90 nm CMOS. From the results, it has been concluded that acceptable tolerance to multiple node disruptions in 90 nm can be achieved through a unique combination of hardened memory and layout design techniques with moderate and calculable levels of layout interleaving.