ESD-Immunity Influence of 60-V pLDMOS by Vertical Floating Polysilicons on the Drain-side STI

Shen-Li Chen, Y. Jhou, Pei-Lin Wu, Sheng-Kai Fan, Po-Lin Lin
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Abstract

In this paper, the area effect of floating polysilicons above the drain-side STI on ESD robustness of high voltage components is studied by 0.25-μm 60-V p-channel LDMOS devices. In general, near the gate and drain-side STI regions have high lateral electric-field peaks. Therefore, some floating polysilicon islands above this STI region can be used to reduce the electric-field peak (to increase the breakdown voltage), and then to evaluate its ability of ESD improvement. There are five kinds of width modulation by the vertical arrangement. From the experimental data, the breakdown voltage of pLDMOSs will increase slightly after embedding these vertical floating polysilicon, the trigger voltage will gradually increase by 0∼2V with increasing the floating polysilicon width. Meanwhile, comparing with the reference device ($I_t2$= 0.758 A), the highest secondary breakdown-current ($I_t2$) can be upgraded to 1.042 A and increased about 38%.
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垂直浮动多晶硅对60 v pLDMOS抗静电性的影响
本文采用0.25-μm - 60 v p沟道LDMOS器件,研究了漏极侧STI上方浮动多晶硅对高压元件ESD稳健性的面积效应。一般而言,栅极附近和漏极侧STI区域具有较高的横向电场峰值。因此,可以在该STI区域上方放置一些浮动多晶硅岛来降低电场峰值(提高击穿电压),进而评价其ESD改善能力。宽度调制有五种垂直排列方式。从实验数据来看,嵌入这些垂直浮动多晶硅后,pLDMOSs的击穿电压会略有升高,触发电压会随着浮动多晶硅宽度的增加而逐渐升高0 ~ 2V。同时,与参考器件($I_t2$= 0.758 A)相比,最高二次击穿电流($I_t2$)可提升至1.042 A,提高约38%。
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