All-copper chip-to-substrate interconnects: Bonding, testing, and design for electrical performance and thermo-mechanical reliability

Abstract

A novel fabrication process has been developed and characterized to create all-copper chip-to-substrate input/output (I/O) connections. Electroless copper plating followed by low temperature annealing in a nitrogen environment was used to create an all-copper bond between copper pillars. The bond strength for the all-copper structure exceeded 165 MPa after annealing at 180degC. During the anneal process, a significant microstructural transformation in the bonded copper-copper interface was observed. The changes were correlated to an increase in the bond strength. The process was characterized with respect to in-plane misalignment of bond sites. Significant planar misalignment, greater than the diameter of the pillars, could be tolerated. Through-plane mismatches between the pillars (pillar gap) as large as 65 mum could be overcome resulting in good pillar-to- pillar bonding. Successful silicon-on-FR4 bonding was achieved with no degradation of the organic board. The mechanical compliance and electrical performance of copper pillar chip-to-substrate interconnects has been modeled. The optimum pillar design is a trade-off between the mechanical compliance of the copper pillars and parasitic electrical effects. Copper pillars with a diameter of 48 mum to 100 mum and height of 508 mum to 657 mum are mechanically compliant and have parasitic inductance and capacitance less than 300 pH and 8.8 fF, respectively. A polymer collar improves the design space to 38 mum to 100 mum diameter and height from 441 mum to 617 mum.