Pub Date : 2010-04-22DOI: 10.1109/TADVP.2010.2041451
W. Tan, I. C. Ume, Ying-Chang Hung, C. F. J. Wu
Out-of-plane displacement (warpage) has been a major thermomechanical reliability concern for board-level electronic packages. Printed wiring board (PWB) and component warpage results principally from CTE mismatch among the materials that make up the PWB assembly (PWBA). Warpage occurring during surface-mount assembly reflow processes and normal operations may lead to severe solder bump reliability problems. In this research, the effect of initial PWB warpage on the low cycle thermal fatigue reliability of the solder bumps in plastic ball grid array (PBGA) packages was studied using experimental and analytical methods. A real-time projection moire warpage measurement system was used to measure the surface topology of PWBA samples at different temperatures. The thermal fatigue reliability of solder bumps was evaluated from experimental thermal cycling tests and finite element simulation results. Three-dimensional (3-D) models of PWBAs with varying board warpage were used to estimate the solder bump fatigue life for different types of PBGAs mounted on PWBs. In order to improve the accuracy of FE results, the projection moire method was used to measure the initial warpage of PWBs, and this warpage was used as a geometric input to the FEM. The simulation results were validated and correlated with the experimental results obtained using the projection moire technique and accelerated thermal cycling tests. An advanced prediction model was generated to predict board level solder bump fatigue life based on the initial PWB warpage, package dimensions and locations, and solder bump materials.
{"title":"Effects of warpage on fatigue reliability of solder bumps: Experimental and analytical studies","authors":"W. Tan, I. C. Ume, Ying-Chang Hung, C. F. J. Wu","doi":"10.1109/TADVP.2010.2041451","DOIUrl":"https://doi.org/10.1109/TADVP.2010.2041451","url":null,"abstract":"Out-of-plane displacement (warpage) has been a major thermomechanical reliability concern for board-level electronic packages. Printed wiring board (PWB) and component warpage results principally from CTE mismatch among the materials that make up the PWB assembly (PWBA). Warpage occurring during surface-mount assembly reflow processes and normal operations may lead to severe solder bump reliability problems. In this research, the effect of initial PWB warpage on the low cycle thermal fatigue reliability of the solder bumps in plastic ball grid array (PBGA) packages was studied using experimental and analytical methods. A real-time projection moire warpage measurement system was used to measure the surface topology of PWBA samples at different temperatures. The thermal fatigue reliability of solder bumps was evaluated from experimental thermal cycling tests and finite element simulation results. Three-dimensional (3-D) models of PWBAs with varying board warpage were used to estimate the solder bump fatigue life for different types of PBGAs mounted on PWBs. In order to improve the accuracy of FE results, the projection moire method was used to measure the initial warpage of PWBs, and this warpage was used as a geometric input to the FEM. The simulation results were validated and correlated with the experimental results obtained using the projection moire technique and accelerated thermal cycling tests. An advanced prediction model was generated to predict board level solder bump fatigue life based on the initial PWB warpage, package dimensions and locations, and solder bump materials.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131203500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-08-18DOI: 10.1109/TCAPT.2009.2014742
Hongjin Jiang, M. Yim, K. Moon, C. Wong
Novel nonconductive adhesives/films (NCAs/NCFs) with carbon nanotubes (CNTs) for high performance interconnects were developed. A small amount of CNTs (0.03 wt%) was dispersed into the NCAs/NCFs to increase the thermal conductivities and at the same time to decrease the coefficient of thermal expansion (CTE) for high thermo-mechanical reliability of the NCAs/NCFs interconnect joints. The thermal mechanical analyzer measurements showed that the CTE value of the 0.03 wt% CNTs filled NCAs/NCFs was significantly decreased. Current-voltage characterizations showed that the current carrying capabilities of the CNTs (0.03 wt%) filled NCAs/NCFs were increased 14% comparing to the unfilled NCAs/NCFs due to the more efficient thermal dissipation.
{"title":"Novel nonconductive adhesives/films with carbon nanotubes for high performance interconnects","authors":"Hongjin Jiang, M. Yim, K. Moon, C. Wong","doi":"10.1109/TCAPT.2009.2014742","DOIUrl":"https://doi.org/10.1109/TCAPT.2009.2014742","url":null,"abstract":"Novel nonconductive adhesives/films (NCAs/NCFs) with carbon nanotubes (CNTs) for high performance interconnects were developed. A small amount of CNTs (0.03 wt%) was dispersed into the NCAs/NCFs to increase the thermal conductivities and at the same time to decrease the coefficient of thermal expansion (CTE) for high thermo-mechanical reliability of the NCAs/NCFs interconnect joints. The thermal mechanical analyzer measurements showed that the CTE value of the 0.03 wt% CNTs filled NCAs/NCFs was significantly decreased. Current-voltage characterizations showed that the current carrying capabilities of the CNTs (0.03 wt%) filled NCAs/NCFs were increased 14% comparing to the unfilled NCAs/NCFs due to the more efficient thermal dissipation.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-08-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114090802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-24DOI: 10.1109/TADVP.2009.2023464
L. McCaslin, S. Yoon, Hangyu Kim, S. Sitaraman
The current trend in the electronics industry is to decrease the size of electronic components while attempting to increase processing power and performance. This is leading to increased interest in thinner printed wiring boards and finer line widths and wire pitches. However, these goals can be hindered by the occurrence of warpage in the manufacturing and assembly process of electronic packages from mismatches in thermomechanical properties of the materials used. Warpage can be problematic as it leads to misalignments during package assembly, reduced tolerances, and a variety of operational failures. Current warpage prediction techniques utilize volume averaging to estimate material properties in layers of copper mixed with interlayer dielectric material. These techniques use copper percentages for an entire layer and do not account for trace orientation. This paper describes the development of a new methodology to predict the warpage of a particular substrate. The developed methodology accounts for both the trace pattern planar density and planar orientation in material property calculations for each layer of a multi-layer substrate. This process has been used to calculate the warpage of actual substrates and the results of using the developed methodology are shown to agree well with experimental data.
{"title":"Methodology for modeling substrate warpage using copper trace pattern implementation","authors":"L. McCaslin, S. Yoon, Hangyu Kim, S. Sitaraman","doi":"10.1109/TADVP.2009.2023464","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2023464","url":null,"abstract":"The current trend in the electronics industry is to decrease the size of electronic components while attempting to increase processing power and performance. This is leading to increased interest in thinner printed wiring boards and finer line widths and wire pitches. However, these goals can be hindered by the occurrence of warpage in the manufacturing and assembly process of electronic packages from mismatches in thermomechanical properties of the materials used. Warpage can be problematic as it leads to misalignments during package assembly, reduced tolerances, and a variety of operational failures. Current warpage prediction techniques utilize volume averaging to estimate material properties in layers of copper mixed with interlayer dielectric material. These techniques use copper percentages for an entire layer and do not account for trace orientation. This paper describes the development of a new methodology to predict the warpage of a particular substrate. The developed methodology accounts for both the trace pattern planar density and planar orientation in material property calculations for each layer of a multi-layer substrate. This process has been used to calculate the warpage of actual substrates and the results of using the developed methodology are shown to agree well with experimental data.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115396671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-21DOI: 10.1109/TCAPT.2009.2014258
Sridhar Canumalla, TI Boulevard
Solder joint reliability issues that can be identified only at the system level are notoriously difficult to resolve in a timely manner using trial and error experimentation alone. The particular case of solder joint reliability of a side switch in a phone subjected to drop-impact is addressed. An approach employing response surface methodology (RSM) is proposed to solve reliability and robust design problems in advanced packaging. In particular, a lOx improvement in the drop test failure rate is demonstrated with a minimum of trial and error experimentation. Technical contributions are a) a novel drop life response function derived from strain energy principles, and b) an approach to address package reliability issues at the system level.
{"title":"Robust design of third level packaging in portable electronics: Solder joint reliability under dynamic mechanical loading","authors":"Sridhar Canumalla, TI Boulevard","doi":"10.1109/TCAPT.2009.2014258","DOIUrl":"https://doi.org/10.1109/TCAPT.2009.2014258","url":null,"abstract":"Solder joint reliability issues that can be identified only at the system level are notoriously difficult to resolve in a timely manner using trial and error experimentation alone. The particular case of solder joint reliability of a side switch in a phone subjected to drop-impact is addressed. An approach employing response surface methodology (RSM) is proposed to solve reliability and robust design problems in advanced packaging. In particular, a lOx improvement in the drop test failure rate is demonstrated with a minimum of trial and error experimentation. Technical contributions are a) a novel drop life response function derived from strain energy principles, and b) an approach to address package reliability issues at the system level.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129716030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-28DOI: 10.1109/ICEPT.2008.4606964
Chen-Chao Wang, C. Kuo, Hung-Hsiang Cheng, C. Chiu, C. Hung
A novel time-domain approach is proposed to synthesize the broadband equivalent circuit model of the power delivery network based on time-domain reflected (TDR)/transmitted (TDT) waveforms either through time-domain reflectometry measurement or finite-difference time-domain (FDTD) simulation. The step responses of the power delivery network are represented in terms of rational functions by the generalized pencil-of-matrix (GPOM) method. According to the step responses, the macro-pi model with each element represented by the optimum pole-residue forms is derived to model the power delivery networks. The equivalent circuits of the macro-pi model are synthesized by a systematic lumped- model extraction technique. The accuracy of this approach is demonstrated both in frequency- and time-domain.
{"title":"Synthesizing SPICE-compatible models of power delivery networks with resonance effect by time-domain waveforms","authors":"Chen-Chao Wang, C. Kuo, Hung-Hsiang Cheng, C. Chiu, C. Hung","doi":"10.1109/ICEPT.2008.4606964","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4606964","url":null,"abstract":"A novel time-domain approach is proposed to synthesize the broadband equivalent circuit model of the power delivery network based on time-domain reflected (TDR)/transmitted (TDT) waveforms either through time-domain reflectometry measurement or finite-difference time-domain (FDTD) simulation. The step responses of the power delivery network are represented in terms of rational functions by the generalized pencil-of-matrix (GPOM) method. According to the step responses, the macro-pi model with each element represented by the optimum pole-residue forms is derived to model the power delivery networks. The equivalent circuits of the macro-pi model are synthesized by a systematic lumped- model extraction technique. The accuracy of this approach is demonstrated both in frequency- and time-domain.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124689596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-06-24DOI: 10.1109/ECTC.2008.4550010
R. Das, F. Egitto, T. Antesberger, F. Marconi, How T. Lin, J. Lauffer, V. Markovich
This paper discusses laser processing of polymer nanocomposites and sol-gel thin films. In particular, recent developments on vertical multilayer embedded capacitors are highlighted. A variety of flexible, transperent nanocomposite thin films ranging from 2 microns to 25 microns thick were processed on copper, or ITO, or organic substrates by large area (330 mm x 470 mm, or 495 mm x 610 mm) liquid coating processes. A frequency-tripled Nd:YAG laser operating at a wavelength of 355 nm was used for the micromachining study. The micromachining was used to generate arrays of variable-thickness capacitors from the nanocomposites. The resultant thickness of the capacitors depends on the number of laser pulses applied. Laser micromachining was also used to make long, deep multiple channels from a capacitance layer. Spacings between two channels act as individual vertical capacitors, and parallel connection eventually produces vertical multilayer capacitors. Optical phototgraphs and SEM micrographs were used to view spacings/channels in the coatings. In the case of sol-gel thin films, micromachining results in various surface morphologies. It can make a "wavy" random 3-D structure, or can make an array of regular 3D patterns (spirals/lines) depending on laser fluence. Altogether, this is a new direction for development of multifunctional nanomaterials.
本文讨论了聚合物纳米复合材料和溶胶-凝胶薄膜的激光加工。特别强调了垂直多层嵌入式电容器的最新发展。通过大面积(330 mm x 470 mm，或495 mm x 610 mm)液体涂层工艺，在铜、ITO或有机衬底上加工了各种柔性、透明的纳米复合薄膜，厚度从2微米到25微米不等。采用三倍频Nd:YAG激光器，工作波长为355nm，进行微加工研究。利用微加工技术将纳米复合材料制成变厚度电容器阵列。电容器的最终厚度取决于所施加的激光脉冲的数量。激光微加工也被用于从电容层制造长而深的多通道。两个通道之间的间隔充当单独的垂直电容器，并联最终产生垂直多层电容器。使用光学照片和扫描电镜显微照片来观察涂层中的间距/通道。在溶胶-凝胶薄膜的情况下，微加工导致各种表面形态。它可以制作一个“波浪”随机三维结构，也可以制作一系列规则的3D图案(螺旋/线)，这取决于激光的影响。总之，这是多功能纳米材料发展的新方向。
{"title":"Laser processing of 3-D structures for embedded and integrated components: An application of flexible and printable nanomaterials in microelectronics","authors":"R. Das, F. Egitto, T. Antesberger, F. Marconi, How T. Lin, J. Lauffer, V. Markovich","doi":"10.1109/ECTC.2008.4550010","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550010","url":null,"abstract":"This paper discusses laser processing of polymer nanocomposites and sol-gel thin films. In particular, recent developments on vertical multilayer embedded capacitors are highlighted. A variety of flexible, transperent nanocomposite thin films ranging from 2 microns to 25 microns thick were processed on copper, or ITO, or organic substrates by large area (330 mm x 470 mm, or 495 mm x 610 mm) liquid coating processes. A frequency-tripled Nd:YAG laser operating at a wavelength of 355 nm was used for the micromachining study. The micromachining was used to generate arrays of variable-thickness capacitors from the nanocomposites. The resultant thickness of the capacitors depends on the number of laser pulses applied. Laser micromachining was also used to make long, deep multiple channels from a capacitance layer. Spacings between two channels act as individual vertical capacitors, and parallel connection eventually produces vertical multilayer capacitors. Optical phototgraphs and SEM micrographs were used to view spacings/channels in the coatings. In the case of sol-gel thin films, micromachining results in various surface morphologies. It can make a \"wavy\" random 3-D structure, or can make an array of regular 3D patterns (spirals/lines) depending on laser fluence. Altogether, this is a new direction for development of multifunctional nanomaterials.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130448408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550222
Y. Lee, P. Crosbie, M. Brown, A. Zbrzezny
Wafer level chip scale packaging (WL-CSP) of connectivity RF components for mobile devices has emerged as a low-cost, enabling technology. WL-CSP devices are electronic components with an exposed die that utilize a ball pitch compatible with standard surface mount technology (SMT) equipments, and common PCB design techniques. WL-CSP allows the devices to be directly mounted on the PCB of portable devices. One concern of adopting WL-CSP for mobile device applications is reliability under dynamic loading conditions, such as phone drop, due to the fragile nature of the exposed silicon die and the unique packaging designs. To mitigate this risk, a set of technical guidelines were established to qualify WL-CSP devices for mobile applications where high strain rate loading is of concern. Several failure modes unique to WL-CSP were addressed and the feasibility of the implementation of WL-CSP, directly mounted on the mobile phone board, without the application of underfill was demonstrated.
{"title":"Reliability of wafer level chip scale packages (WL-CSP) under dynamic loadings","authors":"Y. Lee, P. Crosbie, M. Brown, A. Zbrzezny","doi":"10.1109/ECTC.2008.4550222","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550222","url":null,"abstract":"Wafer level chip scale packaging (WL-CSP) of connectivity RF components for mobile devices has emerged as a low-cost, enabling technology. WL-CSP devices are electronic components with an exposed die that utilize a ball pitch compatible with standard surface mount technology (SMT) equipments, and common PCB design techniques. WL-CSP allows the devices to be directly mounted on the PCB of portable devices. One concern of adopting WL-CSP for mobile device applications is reliability under dynamic loading conditions, such as phone drop, due to the fragile nature of the exposed silicon die and the unique packaging designs. To mitigate this risk, a set of technical guidelines were established to qualify WL-CSP devices for mobile applications where high strain rate loading is of concern. Several failure modes unique to WL-CSP were addressed and the feasibility of the implementation of WL-CSP, directly mounted on the mobile phone board, without the application of underfill was demonstrated.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114986879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550136
A. Paganini, M. Slamani, H. Ding, J. Ferrario, N. Na
The need for radio frequency (RF) test at the wafer level in high-volume production has increased in response to the growing demand for delivering complex "good known dies" (KGD). To keep pace with the market, innovative test solutions need to be developed to meet tighter electrical specifications while maximizing yields and profit margins. This paper presents a versatile test platform built upon low- cost, custom circuitry combined with high performance membrane probes to achieve the lowest test cost per die. In a case study for testing global positioning system (GPS) RF integrated circuit (IC) the proposed methodology implements a quad-site solution to demonstrate superior test time and accuracy compared to traditional approaches.
{"title":"Cost-competitive RF wafer test methodology for high volume production of complex RF ICs","authors":"A. Paganini, M. Slamani, H. Ding, J. Ferrario, N. Na","doi":"10.1109/ECTC.2008.4550136","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550136","url":null,"abstract":"The need for radio frequency (RF) test at the wafer level in high-volume production has increased in response to the growing demand for delivering complex \"good known dies\" (KGD). To keep pace with the market, innovative test solutions need to be developed to meet tighter electrical specifications while maximizing yields and profit margins. This paper presents a versatile test platform built upon low- cost, custom circuitry combined with high performance membrane probes to achieve the lowest test cost per die. In a case study for testing global positioning system (GPS) RF integrated circuit (IC) the proposed methodology implements a quad-site solution to demonstrate superior test time and accuracy compared to traditional approaches.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125212428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550011
Weiping Liu, Paul Bachorik, N. Lee
SAC-Ti alloys exhibited significantly improved drop test performance over not only SAC alloys, but also 63Sn37Pb for ENIG/OSP, NiAu/OSP, and OSP/OSP surface finish systems. The superior performance is attributed to (1) the increased grain size and dendrite size, therefore reduced hardness of solder, (2) inclusion of Ti in the IMC layer, and (3) reduced IMC layer thickness. DSC data indicate that the melting temperature and range were not affected by Ti, but the undercooling was almost completely suppressed. The creep properties of SAC-Ti alloy were comparable with those of SAC alloy, strongly suggesting the gain in drop test performance was not achieved by compromising the thermal fatigue performance. SAC-Mn alloys were also found to outperform SAC alloys and Sn63 for the X/OSP finish combinations studied. In general, SAC-Ti performed equally to or better than SAC-Mn alloys.
{"title":"The superior drop test performance of SAC-Ti solders and its mechanism","authors":"Weiping Liu, Paul Bachorik, N. Lee","doi":"10.1109/ECTC.2008.4550011","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550011","url":null,"abstract":"SAC-Ti alloys exhibited significantly improved drop test performance over not only SAC alloys, but also 63Sn37Pb for ENIG/OSP, NiAu/OSP, and OSP/OSP surface finish systems. The superior performance is attributed to (1) the increased grain size and dendrite size, therefore reduced hardness of solder, (2) inclusion of Ti in the IMC layer, and (3) reduced IMC layer thickness. DSC data indicate that the melting temperature and range were not affected by Ti, but the undercooling was almost completely suppressed. The creep properties of SAC-Ti alloy were comparable with those of SAC alloy, strongly suggesting the gain in drop test performance was not achieved by compromising the thermal fatigue performance. SAC-Mn alloys were also found to outperform SAC alloys and Sn63 for the X/OSP finish combinations studied. In general, SAC-Ti performed equally to or better than SAC-Mn alloys.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116756072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4549952
T. Osborn, A. He, H. Lightsey, P. Kohl
A novel fabrication process has been developed and characterized to create all-copper chip-to-substrate input/output (I/O) connections. Electroless copper plating followed by low temperature annealing in a nitrogen environment was used to create an all-copper bond between copper pillars. The bond strength for the all-copper structure exceeded 165 MPa after annealing at 180degC. During the anneal process, a significant microstructural transformation in the bonded copper-copper interface was observed. The changes were correlated to an increase in the bond strength. The process was characterized with respect to in-plane misalignment of bond sites. Significant planar misalignment, greater than the diameter of the pillars, could be tolerated. Through-plane mismatches between the pillars (pillar gap) as large as 65 mum could be overcome resulting in good pillar-to- pillar bonding. Successful silicon-on-FR4 bonding was achieved with no degradation of the organic board. The mechanical compliance and electrical performance of copper pillar chip-to-substrate interconnects has been modeled. The optimum pillar design is a trade-off between the mechanical compliance of the copper pillars and parasitic electrical effects. Copper pillars with a diameter of 48 mum to 100 mum and height of 508 mum to 657 mum are mechanically compliant and have parasitic inductance and capacitance less than 300 pH and 8.8 fF, respectively. A polymer collar improves the design space to 38 mum to 100 mum diameter and height from 441 mum to 617 mum.
{"title":"All-copper chip-to-substrate interconnects: Bonding, testing, and design for electrical performance and thermo-mechanical reliability","authors":"T. Osborn, A. He, H. Lightsey, P. Kohl","doi":"10.1109/ECTC.2008.4549952","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4549952","url":null,"abstract":"A novel fabrication process has been developed and characterized to create all-copper chip-to-substrate input/output (I/O) connections. Electroless copper plating followed by low temperature annealing in a nitrogen environment was used to create an all-copper bond between copper pillars. The bond strength for the all-copper structure exceeded 165 MPa after annealing at 180degC. During the anneal process, a significant microstructural transformation in the bonded copper-copper interface was observed. The changes were correlated to an increase in the bond strength. The process was characterized with respect to in-plane misalignment of bond sites. Significant planar misalignment, greater than the diameter of the pillars, could be tolerated. Through-plane mismatches between the pillars (pillar gap) as large as 65 mum could be overcome resulting in good pillar-to- pillar bonding. Successful silicon-on-FR4 bonding was achieved with no degradation of the organic board. The mechanical compliance and electrical performance of copper pillar chip-to-substrate interconnects has been modeled. The optimum pillar design is a trade-off between the mechanical compliance of the copper pillars and parasitic electrical effects. Copper pillars with a diameter of 48 mum to 100 mum and height of 508 mum to 657 mum are mechanically compliant and have parasitic inductance and capacitance less than 300 pH and 8.8 fF, respectively. A polymer collar improves the design space to 38 mum to 100 mum diameter and height from 441 mum to 617 mum.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127220076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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