Split Memory Based Memory Architecture with Single-ended High Speed Sensing Circuit to Improve Cache Memory Performance

Abstract

A new Memory design architecture involving Split Column based approach has been discussed in this paper. The target is to improve the Read time performance of Cache Memory by using Read time parallelism property. This involves Splitting a Column into 4 parts (also known as Tiers) during Read operation and reading out all the 4 Tiers simultaneously. So in a single read operation, 4 cells can be read simultaneously, thereby, improving the Bit Rate to 4 times as compared to the conventional design. The design also involves the usage of a new Single ended, High Speed Sensing circuit for SRAM based memory architecture. This Sensing architecture targets to decrease Bit Line to Bit Line coupling effects at the time of Read operation, thereby, improving the per Bitcell Read performance. The proposed architecture exhibits a worst case sensing delay of nearly 0.26ns, showing nearly 2.4 folds improvement in the per Bitcell Read time with respect to the conventional latch type sense amplifier. Overall the proposed design is capable of reading 4 times the data in a much lesser time as compared to the conventional designs.