Implementation of a ASIP for SELP Vocoder At Low Bit Rate of 600bps

Abstract

In this paper, efficient implementation of a 600 bps SELP vocoder having a speech compression function used in the digital mobile communication is presented. This ASIP (application special instruction set processor) of vocoder is designed for high quality multi-rates speech coding algorithm based on SELP model. We adopt VLIW type instruction set and reconfigurable architecture, so those high complexity subprograms can be optimized to get a significant degree of instruction level parallelism. The result of simulation indicates that the algorithms implemented on this chip have higher efficiency than that on universal DSP, while maintaining the original coding quality. The presented chip can implement different kinds of speech coding algorithms and can achieve higher performance, lower complexity and lower cost.