Post-silicon calibration of analog CMOS using phase-change memory cells

Abstract

This paper describes the design of an offset-minimized CMOS comparator with post-manufacturing calibration using non-volatile phase-change random access memory (PCRAM) cells. The digital calibration technique exploits combinatorial redundancy to reduce overall mismatch by selecting an optimal subset from a population of nominally identical elements. PCRAM cells provide switchable resistances that are employed to configure selection. Fabricated in IBM 90 nm CMOS technology with embedded GST (Ge2Sb2Te5)-based PCRAM mushroom cells, a comparator operating at 1V with total power of 55.42μW and input capacitance of 4.41fF achieve 0.5mV input offset voltage with reconfiguration while the corresponding input offset voltage with traditional random offset sizing is 28.5mV.