A pipeline controller for the ATLAS calorimeter

Abstract

One approach to the front-end readout of the ATLAS liquid argon calorimeter is to store data locally in analog pipeline memories at the LHC beam-crossing frequency of 40 MHz. Proto-type pipeline chips using switched capacitor arrays which meet the ATLAS readout requirements exist. These new chips are capable of simultaneous read and write operations, and allow random access to storage locations. To utilize these essential design features requires a substantial amount of fast control and address bookkeeping logic. We have designed a controller capable of operating the pipelines as analog random access memories and that satisfies the ATLAS readout requirements. The pipeline controller manages the data of 256 time samples and provides dead-time free operation up to a trigger rate of 100 kHz, when reading out five time samples per event. This operation allows 2 /spl mu/s for the output reconstruction amplifiers to settle and should be sufficient to achieve the required 13-bit resolution. We are currently proto-typing a second PC-board version of our controller. The implementation of an integrated version based on the same design is in progress.