Optically Interconnected Exchange/bypass Self-routing Node Arrays : Logic And Layout Design

Abstract

Details of the logic design and layout of exchange/bypass self-routing nodes will be presented. Silicon and gallium arsenide baaed technologies are used to layout the nodes. Performance metria of the pixels are quantified. w o n Sorting is recognized as a task for which the benefits of spacevariant non-local optical interconnects provide an increase in performance compared to its electronic counterpart [l]. It was also shown that considerable improvement in the computational time of the sorting can be achieved provided that dedicated hardware is designed in the form of smart pixels [ l j . Consequently, self-routing exchange/bypass modules have been designed in the ATSiT FET-SEED monolithic integration [2] and in the standard CMOS technologies. The smart pixel arrays t,-ill he used in a timemultiplexed multi-stage interconnection network (MIN) in which bitmic sorting is implemented with perfect shuffle interconnects [3]. FET-SEED exchange/bypass self-routing nodes The layout utilizes the monolithic integration technology developed by AT&T [2]. -4rra";s d 4x2 two by two switching nodes and 4x4 two by one switching nodes have been fabricated (see figure 1). The two by two self-routing node is designed to latch at the first difference of the most significant bit of two bit serial optical input data streams. This state is set until an clectrical rcset signal frees the node for the presentation of a new word. This enables one output port to esliihir the maximum of the two input signals. The pixel area is 560pm by 280pm and is expected :o dissipate about 53mW of static electrical power. The output of the two bv one switching riocie (selection of one of the two input signals) is controlled externally by an electrical signal. The pixel area is 280pm by 2 8 0 p ~ . iC and DC measurements will be presented along with t1.e 7 parameters of the FET test devices. CMOS exchange/bypass self-routing nodes The large pixel area and high power density (34 W/cmz) of the GaAs based Iiode allows only an array of 8x8 pixels to be fully operational on a 1 cm2 chip with a heat removal capability oi .SW/cm'. The core of the new routing nodes laid out in 1pm CMOS. n-well double metal