Performance Assessment of Two Stage Operational Transconductance Amplifier in 180nm and 130nm Technology with Optimised Compensation Capacitance

Abstract

This paper illustrates the performance assessment and design of CMOS Two Stage OTA under 130nm and 180nm technology nodes focusing on optimization in compensation capacitance, reduction in power dissipation. The designed circuit operates at two different supply voltages of 1.2V and 1.8V and the input relay is dependent on bias current. In this paper, the device parameters such as AC-Gain, Phase margin, Slew rate, CMRR, ICMR, Output offset voltage, Gain bandwidth, Noise and Power dissipation are theoretically calculated and analysed using LT spice software for 130nm and 180nm technology for given specifications. As the power is a major design parameter, the bias current and supply voltage is varied within the range of respective technology nodes to achieve a minimum power dissipation design. For minimum power design, reduction in bandwidth and stability of the system are major trade-offs. The designed circuit uses a specific compensation methodology for implementing the compensation called Miller compensation. It is used for improving the bandwidth and slew rate of the designed system for various capacitive loads.