Leakage power and delay analysis of LECTOR based CMOS circuits

Abstract

In CMOS circuits, scaling of threshold voltage results in increase of sub-threshold leakage current. According to the International Roadmap of Semiconductor (ITRS), leakage is projected to grow exponentially during the next decade. LECTOR is a technique for designing CMOS gates in order to reduce the leakage current without affecting the dynamic power dissipation. This paper presents the analysis for leakage current and propagation delay of the basic CMOS gates viz. NOT, NAND and NOR gates implementing LECTOR technique.