CA Based Built-In Self-Test Structure for SoC

Abstract

This paper reports synthesis of a built-in self-test logic for the cores integrated into an SoC. The test logic is developed around a nonlinear cellular automata (CA). The CA based scalable PRPG, synthesized in linear time (O(n)), enables the design of such a highly efficient test logic. The cascadable structure of the PRPG is utilized to construct the on-chip Test Pattern Generators (TPGs) for the SoC implementing multiple cores. It avoids the requirement of disparate test hardware for the SoC cores and thereby ensures drastic reduction in the cost of test logic. Extensive experimentation confirms the better efficiency of the proposed test structure than that of the conventional designs, developed around maximal length CA/LFSR.