ASIC design methods using VHDL

Abstract

The design of increasingly more complex custom and semicustom integrated circuits has traditionally forced the introduction of new design methodologies. Formal specifications, top-down design, and design-for-test have become standard practices for IC design teams. The adoption of VHDL (VHSIC Hardware Description Language), as an IEEE standard (IEEE-1076), and the recent availability of design automation tools supporting VHDL, has begun yet another wave of change in the ASIC design process. The author investigates the impact of VHDL on the ASIC design team, as well as on the ASIC manufacturer. It is his intention to identify areas which must be investigated by the ASIC community before incorporating VHDL in the design process.<>