Optimizing gate reticle to silicon flow for variability in low power circuits

Abstract

Ultra-low-power circuits for applications such as biomedical implants and environmental monitoring are being designed to operate in the subthreshold regime. CMOS circuits in this regime are extremely susceptible to manufacturing process variations due to the exponential relationship of transistor sub-threshold drive current (Id) with threshold voltage (Vt) variation. In this paper, we explore the behavior of an inverter ring oscillator that was manufactured using 130nm process technology and operated at low supply voltage (Vdd). We then explore the effects of variations induced due to different aspects of the manufacturing process. Finally, we define the box of safe operation using an existing 130nm CMOS process and the required precision to achieve high yields by optimizing the gate reticle to silicon (Si) flow for the same.