Pub Date : 2010-10-01DOI: 10.1109/DCAS.2010.5955035
D. Webster, J. Cavazos, D. Guy, P. Patchen, D. Lie
This paper describes Built-in Self Test (BiST) techniques used to verify the integrity of a RF CMOS WLAN transceiver by Texas Instruments. The set of BiSTs covers the primary blocks in the RF/analog portion of the radio, verifying the system to be free of defects in a high volume production setting with minimal tester resources. This approach promotes a highly parallel testing opportunity, resulting in reduced test time with lower cost.
{"title":"Structural verification of a WLAN system using Built-in Self Tests","authors":"D. Webster, J. Cavazos, D. Guy, P. Patchen, D. Lie","doi":"10.1109/DCAS.2010.5955035","DOIUrl":"https://doi.org/10.1109/DCAS.2010.5955035","url":null,"abstract":"This paper describes Built-in Self Test (BiST) techniques used to verify the integrity of a RF CMOS WLAN transceiver by Texas Instruments. The set of BiSTs covers the primary blocks in the RF/analog portion of the radio, verifying the system to be free of defects in a high volume production setting with minimal tester resources. This approach promotes a highly parallel testing opportunity, resulting in reduced test time with lower cost.","PeriodicalId":405694,"journal":{"name":"2010 IEEE Dallas Circuits and Systems Workshop","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132119822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/DCAS.2010.5955036
D. Mannath, V. Montaño-Martinez, I. Syllaios, S. Bhatara, M. Attaluri, Z. Parkar, S. Ang
This paper describes the methodology used to replace a conventional FM SNR test on a 65nm Texas Instruments radio with a similar test implemented as a Built-in Self Test (BiST). A traditional R square approach was used for the correlation. Data from various changes that affected/improved the correlation is presented. This approach resulted in test cost savings of around 40%.
{"title":"A reduced-cost Built-in Self Test for an FM receiver","authors":"D. Mannath, V. Montaño-Martinez, I. Syllaios, S. Bhatara, M. Attaluri, Z. Parkar, S. Ang","doi":"10.1109/DCAS.2010.5955036","DOIUrl":"https://doi.org/10.1109/DCAS.2010.5955036","url":null,"abstract":"This paper describes the methodology used to replace a conventional FM SNR test on a 65nm Texas Instruments radio with a similar test implemented as a Built-in Self Test (BiST). A traditional R square approach was used for the correlation. Data from various changes that affected/improved the correlation is presented. This approach resulted in test cost savings of around 40%.","PeriodicalId":405694,"journal":{"name":"2010 IEEE Dallas Circuits and Systems Workshop","volume":"2016 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125725383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/DCAS.2010.5955028
S. Balagopal, Rajaram Mohan Roy, V. Saxena
A third-order single-bit CT-ΔΣ modulator for generic biomedical applications is implemented in a 0.15-μm FD-SOI CMOS process. The overall power efficiency is attained by employing a single-bit quantizer and thus avoiding the mismatch shaping logic. The loop filter coefficients are determined using a systematic design centering approach by accounting for the integrator non-idealities. The single-bit CT-ΔΣ modulator consumes 110μW power from a 1.5-V power supply when clocked at 6.144MHz. The simulation results for the modulator exhibit a dynamic range of 94.4 dB and peak SNDR of 92.4 dB for 6 kHz signal bandwidth. The figure of merit (FoM) of this third-order, single-bit CT-ΔΣ modulator is 0.271pJ/level.
{"title":"A 110μW single-bit continuous-time ΔΣ converter with 92.5dB dynamic range","authors":"S. Balagopal, Rajaram Mohan Roy, V. Saxena","doi":"10.1109/DCAS.2010.5955028","DOIUrl":"https://doi.org/10.1109/DCAS.2010.5955028","url":null,"abstract":"A third-order single-bit CT-ΔΣ modulator for generic biomedical applications is implemented in a 0.15-μm FD-SOI CMOS process. The overall power efficiency is attained by employing a single-bit quantizer and thus avoiding the mismatch shaping logic. The loop filter coefficients are determined using a systematic design centering approach by accounting for the integrator non-idealities. The single-bit CT-ΔΣ modulator consumes 110μW power from a 1.5-V power supply when clocked at 6.144MHz. The simulation results for the modulator exhibit a dynamic range of 94.4 dB and peak SNDR of 92.4 dB for 6 kHz signal bandwidth. The figure of merit (FoM) of this third-order, single-bit CT-ΔΣ modulator is 0.271pJ/level.","PeriodicalId":405694,"journal":{"name":"2010 IEEE Dallas Circuits and Systems Workshop","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116449893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/DCAS.2010.5955041
C. Montiel, Parkash S. Arora
This paper describes the steps taken to convert a low-volume test solution into an efficient, low-cost, high-volume Automated Test Equipment (ATE) solution. At the beginning of the project, two different devices, sharing the same footprint, designed for broadband wireless access using the IEEE 802.16 d/e protocols at different bands, were production tested using a hand-loaded low-volume test solution. To increase production throughput and reduce cost, a high-volume ATE solution was proposed and implemented for both devices. In order to utilize the same load board and improve performance for each device, dual printed circuit board (PCB) baluns were designed, simulated, built, and characterized. The baluns were switched under software control depending on the type of device tested. Because the ATE load board was much more complex than the manual test board, we devised a simple method for de-embedding path loss when only one port was accessible. The solution greatly simplified production testing and increased test coverage and throughput.
{"title":"A dual device load board with dual switched printed baluns","authors":"C. Montiel, Parkash S. Arora","doi":"10.1109/DCAS.2010.5955041","DOIUrl":"https://doi.org/10.1109/DCAS.2010.5955041","url":null,"abstract":"This paper describes the steps taken to convert a low-volume test solution into an efficient, low-cost, high-volume Automated Test Equipment (ATE) solution. At the beginning of the project, two different devices, sharing the same footprint, designed for broadband wireless access using the IEEE 802.16 d/e protocols at different bands, were production tested using a hand-loaded low-volume test solution. To increase production throughput and reduce cost, a high-volume ATE solution was proposed and implemented for both devices. In order to utilize the same load board and improve performance for each device, dual printed circuit board (PCB) baluns were designed, simulated, built, and characterized. The baluns were switched under software control depending on the type of device tested. Because the ATE load board was much more complex than the manual test board, we devised a simple method for de-embedding path loss when only one port was accessible. The solution greatly simplified production testing and increased test coverage and throughput.","PeriodicalId":405694,"journal":{"name":"2010 IEEE Dallas Circuits and Systems Workshop","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116572028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/DCAS.2010.5955032
A. Parikh, M. Kulkarni
Ultra-low-power circuits for applications such as biomedical implants and environmental monitoring are being designed to operate in the subthreshold regime. CMOS circuits in this regime are extremely susceptible to manufacturing process variations due to the exponential relationship of transistor sub-threshold drive current (Id) with threshold voltage (Vt) variation. In this paper, we explore the behavior of an inverter ring oscillator that was manufactured using 130nm process technology and operated at low supply voltage (Vdd). We then explore the effects of variations induced due to different aspects of the manufacturing process. Finally, we define the box of safe operation using an existing 130nm CMOS process and the required precision to achieve high yields by optimizing the gate reticle to silicon (Si) flow for the same.
{"title":"Optimizing gate reticle to silicon flow for variability in low power circuits","authors":"A. Parikh, M. Kulkarni","doi":"10.1109/DCAS.2010.5955032","DOIUrl":"https://doi.org/10.1109/DCAS.2010.5955032","url":null,"abstract":"Ultra-low-power circuits for applications such as biomedical implants and environmental monitoring are being designed to operate in the subthreshold regime. CMOS circuits in this regime are extremely susceptible to manufacturing process variations due to the exponential relationship of transistor sub-threshold drive current (Id) with threshold voltage (Vt) variation. In this paper, we explore the behavior of an inverter ring oscillator that was manufactured using 130nm process technology and operated at low supply voltage (Vdd). We then explore the effects of variations induced due to different aspects of the manufacturing process. Finally, we define the box of safe operation using an existing 130nm CMOS process and the required precision to achieve high yields by optimizing the gate reticle to silicon (Si) flow for the same.","PeriodicalId":405694,"journal":{"name":"2010 IEEE Dallas Circuits and Systems Workshop","volume":"76 9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127395460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/DCAS.2010.5955040
Yasaswini Sudarsanam, A. Rajagopalan
The importance of the metrics of power vs. performance and area vs. performance can hardly be overstated in the context of timing closure on deep submicron designs. This paper describes how useful clock skew is handled post placement to fix timing without compromising the robustness of the clock tree. A novel method of automation is proposed where useful skew is calculated and applied across the design after evaluating the impact of skew introduction on multiple modes and corners, a limiting factor for most production tools. It is described further how the technique was deployed on a 45 nm multi-million gate imaging subsystem to improve power by 50% and area by as much as 90% in portions of the design. The paper concludes with a comparison of results from traditional setup and hold fixing vs. useful skew adjustment.
{"title":"Clock skew automation for power and area reduction in deep sub micron designs","authors":"Yasaswini Sudarsanam, A. Rajagopalan","doi":"10.1109/DCAS.2010.5955040","DOIUrl":"https://doi.org/10.1109/DCAS.2010.5955040","url":null,"abstract":"The importance of the metrics of power vs. performance and area vs. performance can hardly be overstated in the context of timing closure on deep submicron designs. This paper describes how useful clock skew is handled post placement to fix timing without compromising the robustness of the clock tree. A novel method of automation is proposed where useful skew is calculated and applied across the design after evaluating the impact of skew introduction on multiple modes and corners, a limiting factor for most production tools. It is described further how the technique was deployed on a 45 nm multi-million gate imaging subsystem to improve power by 50% and area by as much as 90% in portions of the design. The paper concludes with a comparison of results from traditional setup and hold fixing vs. useful skew adjustment.","PeriodicalId":405694,"journal":{"name":"2010 IEEE Dallas Circuits and Systems Workshop","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128032794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/DCAS.2010.5955034
Mohammad Rahman, R. Afonso, Hiran Tennakoon, C. Sechen
Assuming arbitrary (continuous cell sizes) we have achieved global minimization of the total transistor sizes needed to achieve a delay goal, thus minimizing dynamic power (and reducing leakage power). We then developed a feasible branch-and-bound algorithm that maps the continuous sizes to the discrete sizes available in the standard cell library. Results show that a well-designed library gives results close to the optimal continuous size results. We developed a new approach to threshold voltage selection, among options available in a cell library. This algorithm is applied after optimal gate size selection, and raises threshold voltages as much as possible while strictly maintaining the delay goal. In addition, we identified the optimal set of (just 8) combinational functions in a physical cell library. These constitute the most power efficient cells needed to implement combinational logic. On the other hand, the synthesis library is much more complex, consisting of cells that are combinations of the physical library cells. This is advantageous since the constituent cells (of a more complex synthesis cell) are placed next to each other in the layout, ensuring minimal wire length between them. Since wire delay is a significant portion of total path delay for contemporary circuits, having complex cells in synthesis is important. But, for power efficiency, the physical cells must be rather simple, with no more than two transistors in series for any cell. The entire cell size and threshold voltage selection flow is efficient, with an ability to handle multi-million-gate commercial designs. After using state-of-the-art commercial synthesis, the application of our design automation tools and library results in a dynamic power reduction of 25–35% and leakage power reduction by 50–70% for large logic blocks.
{"title":"Design automation tools and libraries for low power digital design","authors":"Mohammad Rahman, R. Afonso, Hiran Tennakoon, C. Sechen","doi":"10.1109/DCAS.2010.5955034","DOIUrl":"https://doi.org/10.1109/DCAS.2010.5955034","url":null,"abstract":"Assuming arbitrary (continuous cell sizes) we have achieved global minimization of the total transistor sizes needed to achieve a delay goal, thus minimizing dynamic power (and reducing leakage power). We then developed a feasible branch-and-bound algorithm that maps the continuous sizes to the discrete sizes available in the standard cell library. Results show that a well-designed library gives results close to the optimal continuous size results. We developed a new approach to threshold voltage selection, among options available in a cell library. This algorithm is applied after optimal gate size selection, and raises threshold voltages as much as possible while strictly maintaining the delay goal. In addition, we identified the optimal set of (just 8) combinational functions in a physical cell library. These constitute the most power efficient cells needed to implement combinational logic. On the other hand, the synthesis library is much more complex, consisting of cells that are combinations of the physical library cells. This is advantageous since the constituent cells (of a more complex synthesis cell) are placed next to each other in the layout, ensuring minimal wire length between them. Since wire delay is a significant portion of total path delay for contemporary circuits, having complex cells in synthesis is important. But, for power efficiency, the physical cells must be rather simple, with no more than two transistors in series for any cell. The entire cell size and threshold voltage selection flow is efficient, with an ability to handle multi-million-gate commercial designs. After using state-of-the-art commercial synthesis, the application of our design automation tools and library results in a dynamic power reduction of 25–35% and leakage power reduction by 50–70% for large logic blocks.","PeriodicalId":405694,"journal":{"name":"2010 IEEE Dallas Circuits and Systems Workshop","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121752619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/DCAS.2010.5955042
J. Mehta, I. Bashir, Vasile Zoicas, Yongtao Wang, O. Eliezer, K. Waheed, Mitch Entezari, S. Larson, D. Shrestha, S. Rezeq, R. Staszewski, P. Balsara
A built-in self-calibration and self-compensation scheme for a digital power pre-amplifier (DPA) of a mobile handset transceiver is proposed. It allows accurate internal measurements of the amplitude and phase distortions experienced in the DPA using the on-chip receiver and processor. A dynamic range of over 60 dB is achieved using multiple gain settings in the receiver. The proposed scheme, in conjunction with the transceiver's digital architecture, is demonstrated in a 65-nm CMOS GSM/EDGE radio, where it allows for accurate and cost-effective self-calibration to be performed in less than 0.1 s.
{"title":"Self-calibration of a power pre-amplifier in a digital polar transmitter","authors":"J. Mehta, I. Bashir, Vasile Zoicas, Yongtao Wang, O. Eliezer, K. Waheed, Mitch Entezari, S. Larson, D. Shrestha, S. Rezeq, R. Staszewski, P. Balsara","doi":"10.1109/DCAS.2010.5955042","DOIUrl":"https://doi.org/10.1109/DCAS.2010.5955042","url":null,"abstract":"A built-in self-calibration and self-compensation scheme for a digital power pre-amplifier (DPA) of a mobile handset transceiver is proposed. It allows accurate internal measurements of the amplitude and phase distortions experienced in the DPA using the on-chip receiver and processor. A dynamic range of over 60 dB is achieved using multiple gain settings in the receiver. The proposed scheme, in conjunction with the transceiver's digital architecture, is demonstrated in a 65-nm CMOS GSM/EDGE radio, where it allows for accurate and cost-effective self-calibration to be performed in less than 0.1 s.","PeriodicalId":405694,"journal":{"name":"2010 IEEE Dallas Circuits and Systems Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123170281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/DCAS.2010.5955033
Mario Lok, Ku He, Murari Mani, C. Caramanis, M. Orshansky
In many digital designs, multi-stage tapered buffers are needed to drive large capacitive loads. These buffers contribute a significant percentage of overall power. In this paper, we propose two novel tunable buffer designs that enable power reduction in the presence of process variation. A strategy to derive the optimal buffer size and tuning rule in post-silicon phase is developed. By comparing several tunable buffer circuit topologies, we also demonstrate the tradeoffs in tunable buffer topology selection as a function of switching activity, timing requirements, and the magnitude of process variation. Using a combination of HSPICE simulations and our optimization algorithm, we show that up to 30% average power reduction can be achieved with the proposed buffer structures.
{"title":"Design of power-optimal buffers tunable to process variability","authors":"Mario Lok, Ku He, Murari Mani, C. Caramanis, M. Orshansky","doi":"10.1109/DCAS.2010.5955033","DOIUrl":"https://doi.org/10.1109/DCAS.2010.5955033","url":null,"abstract":"In many digital designs, multi-stage tapered buffers are needed to drive large capacitive loads. These buffers contribute a significant percentage of overall power. In this paper, we propose two novel tunable buffer designs that enable power reduction in the presence of process variation. A strategy to derive the optimal buffer size and tuning rule in post-silicon phase is developed. By comparing several tunable buffer circuit topologies, we also demonstrate the tradeoffs in tunable buffer topology selection as a function of switching activity, timing requirements, and the magnitude of process variation. Using a combination of HSPICE simulations and our optimization algorithm, we show that up to 30% average power reduction can be achieved with the proposed buffer structures.","PeriodicalId":405694,"journal":{"name":"2010 IEEE Dallas Circuits and Systems Workshop","volume":"2016 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131239866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/DCAS.2010.5955029
U. Nukala, Kye-Shin Lee
A compact current steering DAC with component swapping calibration is proposed. By using different reference currents for the upper and lower bits conversion, the number of current sources can be considerably reduced. Therefore, an 8-bit DAC can be realized using only four binary weighted current sources, which reduces the effect of current source mismatch. Furthermore, the performance degradation due to resistor mismatch between the reference current generator and output network is calibrated by swapping the two resistors, and taking the average to obtain the final output of the DAC. As a result, the proposed scheme enables the DAC design using resistors with even poor matching. Circuit level simulation results show the INL is 0.85 LSB with 10% resistor and 1% capacitor mismatch, respectively.
{"title":"A compact current steering DAC with component swapping calibration","authors":"U. Nukala, Kye-Shin Lee","doi":"10.1109/DCAS.2010.5955029","DOIUrl":"https://doi.org/10.1109/DCAS.2010.5955029","url":null,"abstract":"A compact current steering DAC with component swapping calibration is proposed. By using different reference currents for the upper and lower bits conversion, the number of current sources can be considerably reduced. Therefore, an 8-bit DAC can be realized using only four binary weighted current sources, which reduces the effect of current source mismatch. Furthermore, the performance degradation due to resistor mismatch between the reference current generator and output network is calibrated by swapping the two resistors, and taking the average to obtain the final output of the DAC. As a result, the proposed scheme enables the DAC design using resistors with even poor matching. Circuit level simulation results show the INL is 0.85 LSB with 10% resistor and 1% capacitor mismatch, respectively.","PeriodicalId":405694,"journal":{"name":"2010 IEEE Dallas Circuits and Systems Workshop","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127581717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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