Hot electron induced channel length shortening model and its impact on HEIP in PMOS

1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings Pub Date : 1995-11-06 DOI:10.1109/TENCON.1995.496382

J. Park, Y.T. Kim, D. Kim, S. Hong, C.G. Yu

引用次数: 0

Abstract

A new analytical model based on a pseudo two dimensional model is presented for the hot electron induced channel length shortening (/spl Delta/L/sub H/) of PMOSFET. It has been founded that /spl Delta/L/sub H/ is a logarithmic function of both the stress time and the degradation of punchthrough voltage, and is also a linear function of the degradation of the drain current. /spl Delta/L/sub H/ can be predicted from the measurement of the gate current (/spl Delta/L/sub H//spl prop/I/sub g//sup n/) and can thus be used for the current calculation of a degraded PMOSFET.

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热电子诱导的PMOS通道长度缩短模型及其对HEIP的影响

提出了一种基于伪二维模型的PMOSFET热电子诱导通道长度缩短(/spl Delta/L/sub H/)的新解析模型。发现/spl δ /L/sub H/是应力时间和击穿电压退化的对数函数，也是漏极电流退化的线性函数。/spl Delta/L/sub H/可以从门电流的测量中预测(/spl Delta/L/sub H//spl prop/I/sub g//sup n/)，因此可以用于退化PMOSFET的电流计算。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings

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