Reliability issues for silicon-on-insulator

Abstract

Understanding the reliability implications for silicon-on-insulator (SOI) is crucial for its use in ULSI technology. The fabrication process of SOI material and the device operation, due to the buried oxide (BOX) layer, could present additional concerns for meeting reliability requirements. In this paper, we discuss the reliability issues with silicon-on-insulator (SOI) technology. We focus on partially depleted (PD) SOI CMOS technology using SIMOX and bonded substrate material. We compare the reliability mechanisms, namely channel hot electron (CHE), gate oxide time dependent dielectric breakdown (TDDB), bias temperature stress (BTS) and plasma-induced charging damage, to bulk CMOS. In addition, results from high performance microprocessors subjected to burn-in stress are presented. Finally, we discuss the circuitry implications for electrostatic discharge (ESD).