On-chip process variation-tracking through an all-digital monitoring architecture

Abstract

In sub-nanometer complementary metal oxide semiconductor (CMOS) technologies, process variability strongly affects the fabrication yield. To face this problem, post-silicon adaptive approaches have been proposed as a promising solution. However, their actual implementation requires the availability of effective monitoring architectures that can sense and sample process variation across the die. In this study, the authors present a sensor circuit for capturing on-chip variations owing to the fabrication process. The proposed solution is based on the concept of ‘variation amplification’ and uses the propagation delay measurement through a pass-transistor chain. Our monitor architecture, which consists of a self-contained cell containing N- and P-type sensors along with an all-digital delay measurement circuitry, is able to capture local variations of negative metal oxide semiconductors and positive metal oxide semiconductors transistors individually, therefore enabling fine tuning of the circuit. The authors also propose an array-based integration of the monitors, where the sensors are placed in a different location of the die and connected together with the scan–chain to distribute the sampled data. Detailed SPICE level simulations conducted on an industrial 45-nm CMOS technology demonstrate the sensing capability of the proposed architecture and the effectiveness of the on-chip all-digital measurement process.