On CMOS Memory Design in Low Supply Voltage for Integrated Biosensor Applications

Abstract

Storage arrays are widely used in integrated biosensor systems to store detected signals before and after they are processed. As integrated biosensor systems often require very low power consumption to extend battery life and to maintain low cost, power consumption for storage arrays in integrated biosensor systems should be kept low, whereas the speed requirement is usually not high such that state-of-the-art IC technology is not usually needed. This paper presents the results of our investigation of designing low power memory structures in sub 1-V operation with high reliability for biosensor systems. Rather than using the state-of-the-art 45nm/32nm technology, 0.18 um CMOS technology is used for the design to keep the overall cost down while achieving read and write performance of 200MHz cycle rate. The results show that the use of body back bias in systems with low supply voltage can improve memory's static noise margin (SNM) and memory write performance by as much as 25%.