A Novel Three-Dimensional 6T-SRAM Cell Featuring Vertical Transistors and 24F2 Layout Area

Abstract

A novel three-dimensional structure for 6-transistor static random access memory (SRAM) cell composed of vertical gate-all-around transistors is proposed. A three-layer design for the cell is laid out with an area of 24F2, which is multiple times denser than conventional cell design. Significant cost-per-function benefits are thus expected. Buried power rail design facilitates routing in the ultra-compact cell. A novel monolithic process sequence to realize the cell utilizes 9 masks, somewhat increasing processing cost as compared to two-dimensional SRAM. The vertical gate-all-around transistor may either have conventional junction or junctionless design, the latter implying simpler fabrication process. Reasonable cell characteristics is demonstrated with TCAD simulation down to a supply voltage of 0.5V.