Multiple-valued logic approach for a systolic AB/sup 2/ circuit in Galois field

Abstract

In public key cryptosystems and error-correcting codes over Galois fields, the AB/sup 2/ operation is an efficient basic operation. The current paper presents the use of multiple-valued logic (MVL) approach to minimize the systolic architecture of AB/sup 2/ algorithm over binary Galois fields. The design is composed of four basic cells connected in a pipelined fashion. The circuit has been simulated using affirma analog circuit design environment tool supplied by Cadence, and it has shown to perform correctly. The quaternary circuit for GF((2/sup 2/)/sup 2/) shows a significant amount of savings in both transistor count and the number of connections compared to the one that uses the binary field GF(2/sup 4/).