This paper presents a statistical approach for fast comparison of multiple-valued logic (MVL) designs. Since there are no standard benchmark functions available for MVL, the benchmark functions for binary logic were used for performance analysis of MVL circuits. An alternative would be to test all the possible multiple-valued logic functions for different input variables. However, the testing process is a very time consuming. Monte Carlo simulation (MCS) has been used in the past to explore systems involving large range of parameters. By using MCS, it is found that 150 random functions are sufficient to obtain an average circuit size of all possible 2-input, 4-valued logic functions.
{"title":"Estimation of average multiple-valued logic circuit size using Monte Carlo simulation technique","authors":"D. Teng, R. Bolton","doi":"10.1109/ISMVL.2005.17","DOIUrl":"https://doi.org/10.1109/ISMVL.2005.17","url":null,"abstract":"This paper presents a statistical approach for fast comparison of multiple-valued logic (MVL) designs. Since there are no standard benchmark functions available for MVL, the benchmark functions for binary logic were used for performance analysis of MVL circuits. An alternative would be to test all the possible multiple-valued logic functions for different input variables. However, the testing process is a very time consuming. Monte Carlo simulation (MCS) has been used in the past to explore systems involving large range of parameters. By using MCS, it is found that 150 random functions are sufficient to obtain an average circuit size of all possible 2-input, 4-valued logic functions.","PeriodicalId":340578,"journal":{"name":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114571057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposes analog soft-information decoding circuits for error protection in multi-level memories, providing stronger error protection than binary error-correcting codes. The cell capacitance can then be reduced without an increase in the soft error rate. Analog decoders perform soft-information decoding with very low area requirements. We introduce a multi-level analog interface circuit for analog decoding of MLDRAM signals. We also apply basic information theory to reveal the possibilities and limitations of coding in multi-level memories.
{"title":"Analog soft decoding for multi-level memories","authors":"C. Winstead","doi":"10.1109/ISMVL.2005.8","DOIUrl":"https://doi.org/10.1109/ISMVL.2005.8","url":null,"abstract":"This paper proposes analog soft-information decoding circuits for error protection in multi-level memories, providing stronger error protection than binary error-correcting codes. The cell capacitance can then be reduced without an increase in the soft error rate. Analog decoders perform soft-information decoding with very low area requirements. We introduce a multi-level analog interface circuit for analog decoding of MLDRAM signals. We also apply basic information theory to reveal the possibilities and limitations of coding in multi-level memories.","PeriodicalId":340578,"journal":{"name":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129593669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Let k/spl ges/2, k be a k-element set, /spl rho//sub 1/ and /spl rho//sub 2/ two relations on k and let /spl rho//sub 1//spl ominus//spl rho//sub 2/ be the concatenation of /spl rho//sub 1/ and /spl rho//sub 2/. We study the link between the partial clones pPol /spl rho//sub 1//spl cap/pPol /spl rho//sub 2/ and pPol (/spl rho//sub 1//spl ominus//spl rho//sub 2/). Using results arising from this study we address the following problem: given two maximal partial clones M/sub 1/ and M/sub 2/ over k, under what conditions is the partial clone M/sub 1//spl cap/M/sub 2/ covered by M/sub 1/ or by M/sub 1/? So far the research in this direction was focused on partial clones of Boolean functions and on Slupecki type maximal partial clones.
{"title":"Partial clones determined by concatenated relations","authors":"L. Haddad, I. Rosenberg","doi":"10.1109/ISMVL.2005.36","DOIUrl":"https://doi.org/10.1109/ISMVL.2005.36","url":null,"abstract":"Let k/spl ges/2, k be a k-element set, /spl rho//sub 1/ and /spl rho//sub 2/ two relations on k and let /spl rho//sub 1//spl ominus//spl rho//sub 2/ be the concatenation of /spl rho//sub 1/ and /spl rho//sub 2/. We study the link between the partial clones pPol /spl rho//sub 1//spl cap/pPol /spl rho//sub 2/ and pPol (/spl rho//sub 1//spl ominus//spl rho//sub 2/). Using results arising from this study we address the following problem: given two maximal partial clones M/sub 1/ and M/sub 2/ over k, under what conditions is the partial clone M/sub 1//spl cap/M/sub 2/ covered by M/sub 1/ or by M/sub 1/? So far the research in this direction was focused on partial clones of Boolean functions and on Slupecki type maximal partial clones.","PeriodicalId":340578,"journal":{"name":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129912655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Prior proposed a three-valued modal logic Q as a "correct" modal logic from his philosophical motivations. Unfortunately, Prior's Q and many-valued modal logic have been neglected in the tradition of many-valued and modal logic. In this paper, we introduce a version of three-valued Kripke semantics for Q, which aims to establish Prior's ideas based on possible worlds. We investigate formal properties of Q and prove the completeness theorem of Q. We also compare our approach with others.
{"title":"On Prior's three-valued modal logic Q","authors":"S. Akama, Y. Nagata","doi":"10.1109/ISMVL.2005.33","DOIUrl":"https://doi.org/10.1109/ISMVL.2005.33","url":null,"abstract":"Prior proposed a three-valued modal logic Q as a \"correct\" modal logic from his philosophical motivations. Unfortunately, Prior's Q and many-valued modal logic have been neglected in the tradition of many-valued and modal logic. In this paper, we introduce a version of three-valued Kripke semantics for Q, which aims to establish Prior's ideas based on possible worlds. We investigate formal properties of Q and prove the completeness theorem of Q. We also compare our approach with others.","PeriodicalId":340578,"journal":{"name":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130471134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A number of new quaternary linearly independent helix transformations have been introduced here. These transformations have close relations and properties among each other that have been described. The experimental results also show the advantage of selected class of introduced transformations in processing quaternary benchmark functions when compared with quaternary Reed-Muller transform not only by obtaining more zero spectral coefficients but also by speeding up their calculation time.
{"title":"Properties and relations of quaternary linearly independent helix transformations","authors":"Cheng Fu, B. Falkowski","doi":"10.1109/ISMVL.2005.39","DOIUrl":"https://doi.org/10.1109/ISMVL.2005.39","url":null,"abstract":"A number of new quaternary linearly independent helix transformations have been introduced here. These transformations have close relations and properties among each other that have been described. The experimental results also show the advantage of selected class of introduced transformations in processing quaternary benchmark functions when compared with quaternary Reed-Muller transform not only by obtaining more zero spectral coefficients but also by speeding up their calculation time.","PeriodicalId":340578,"journal":{"name":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","volume":"1118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133842886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
For any finite set A, the partial clone lattice on A is embedded into the partial hyperclone lattice on A. It is shown that there are maximal intervals in the partial hyperclone lattice and there are four minimal partial hyperclones such that their join contains all partial hyperoperations. It is proved in (T. Drescher et al., 2001) that the mapping /spl lambda/ from the lattice of partial hyperclones on A into the lattice of clones of operations on P(A) defined by /spl lambda/(C)=/spl delta/(C/sup #/), where /spl delta/(C/sup #/) is the clone of operations on P(A) generated by C/sup #/, is an order embedding, but not a full one. In this paper, it is proved that there are continuum many clones of operations on P(A) that are in the interval [/spl lambda/(J/sub A/), /spl lambda/(Hp/sub A/)] but these are not in the set im/spl lambda/ of all images of the mapping /spl lambda/, where J/sub A/ is the set of all (partial) hyperprojections and Hp/sub A/ is the set of all partial hyperoperations on A.
{"title":"On the partial hyperclone lattice","authors":"J. Pantović, G. Vojvodic","doi":"10.1109/ISMVL.2005.34","DOIUrl":"https://doi.org/10.1109/ISMVL.2005.34","url":null,"abstract":"For any finite set A, the partial clone lattice on A is embedded into the partial hyperclone lattice on A. It is shown that there are maximal intervals in the partial hyperclone lattice and there are four minimal partial hyperclones such that their join contains all partial hyperoperations. It is proved in (T. Drescher et al., 2001) that the mapping /spl lambda/ from the lattice of partial hyperclones on A into the lattice of clones of operations on P(A) defined by /spl lambda/(C)=/spl delta/(C/sup #/), where /spl delta/(C/sup #/) is the clone of operations on P(A) generated by C/sup #/, is an order embedding, but not a full one. In this paper, it is proved that there are continuum many clones of operations on P(A) that are in the interval [/spl lambda/(J/sub A/), /spl lambda/(Hp/sub A/)] but these are not in the set im/spl lambda/ of all images of the mapping /spl lambda/, where J/sub A/ is the set of all (partial) hyperprojections and Hp/sub A/ is the set of all partial hyperoperations on A.","PeriodicalId":340578,"journal":{"name":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124521214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In public key cryptosystems and error-correcting codes over Galois fields, the AB/sup 2/ operation is an efficient basic operation. The current paper presents the use of multiple-valued logic (MVL) approach to minimize the systolic architecture of AB/sup 2/ algorithm over binary Galois fields. The design is composed of four basic cells connected in a pipelined fashion. The circuit has been simulated using affirma analog circuit design environment tool supplied by Cadence, and it has shown to perform correctly. The quaternary circuit for GF((2/sup 2/)/sup 2/) shows a significant amount of savings in both transistor count and the number of connections compared to the one that uses the binary field GF(2/sup 4/).
{"title":"Multiple-valued logic approach for a systolic AB/sup 2/ circuit in Galois field","authors":"Nabil Abu-Khader, P. Siy","doi":"10.1109/ISMVL.2005.30","DOIUrl":"https://doi.org/10.1109/ISMVL.2005.30","url":null,"abstract":"In public key cryptosystems and error-correcting codes over Galois fields, the AB/sup 2/ operation is an efficient basic operation. The current paper presents the use of multiple-valued logic (MVL) approach to minimize the systolic architecture of AB/sup 2/ algorithm over binary Galois fields. The design is composed of four basic cells connected in a pipelined fashion. The circuit has been simulated using affirma analog circuit design environment tool supplied by Cadence, and it has shown to perform correctly. The quaternary circuit for GF((2/sup 2/)/sup 2/) shows a significant amount of savings in both transistor count and the number of connections compared to the one that uses the binary field GF(2/sup 4/).","PeriodicalId":340578,"journal":{"name":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127488916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Degawa, T. Aoki, H. Inokawa, T. Higuchi, Yasuo Takahashi
This paper presents a circuit design of a two-bit-per-cell content-addressable memory (CAM) using single-electron transistors (SETs). The key ideas of the proposed CAM architecture are (i) four-level data storage function implementing by a SET-based static memory cell and (ii) four-level data matching function employing periodic drain-current characteristics of SETs with dynamic phase-shift control. A simple multi-gate SET can be used to realize four-level data matching within a compact CAM cell circuit. As a result, the proposed two-bit-per-cell CAM architecture reduces the number of transistors to 1/3 compared with the conventional CAM architecture.
{"title":"A two-bit-per-cell content-addressable memory using single-electron transistors","authors":"K. Degawa, T. Aoki, H. Inokawa, T. Higuchi, Yasuo Takahashi","doi":"10.1109/ISMVL.2005.6","DOIUrl":"https://doi.org/10.1109/ISMVL.2005.6","url":null,"abstract":"This paper presents a circuit design of a two-bit-per-cell content-addressable memory (CAM) using single-electron transistors (SETs). The key ideas of the proposed CAM architecture are (i) four-level data storage function implementing by a SET-based static memory cell and (ii) four-level data matching function employing periodic drain-current characteristics of SETs with dynamic phase-shift control. A simple multi-gate SET can be used to realize four-level data matching within a compact CAM cell circuit. As a result, the proposed two-bit-per-cell CAM architecture reduces the number of transistors to 1/3 compared with the conventional CAM architecture.","PeriodicalId":340578,"journal":{"name":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","volume":"82 9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129968457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present an abstract axiomatization of generalized entropy using the notion of ordinal number and the new concept of systemic set of equivalence relations. The axiomatization applies to arbitrary sets and extends previous results obtained for the finite case.
{"title":"An abstract axiomatization of the notion of entropy","authors":"I. Rosenberg, D. Simovici","doi":"10.1109/ISMVL.2005.7","DOIUrl":"https://doi.org/10.1109/ISMVL.2005.7","url":null,"abstract":"We present an abstract axiomatization of generalized entropy using the notion of ordinal number and the new concept of systemic set of equivalence relations. The axiomatization applies to arbitrary sets and extends previous results obtained for the finite case.","PeriodicalId":340578,"journal":{"name":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131240067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
E. Zaitseva, V. Levashenko, K. Matiaško, S. Puuronen
A multi-state system k-out-of-n is one of basic models in reliability analysis. In this system, k is the minimum number of n components that must work for the system to work and both the system and its components can have more than two states. A structure function declares relation between system and component states uniquely. New algorithm for reliability analysis of the k-out-of-n multi-state system is proposed in this paper. We use two tools for examine this system: (a) structure function for the system description; (b) direct partial logic derivatives for analysis this system. New algorithm for reliability analysis of the multi-state system k-out-of-n is allowed to calculate the probability of influence i-th system component on the system breakdown or its repairing and the probability of a modification of multi-state system reliability at a change one of the system component states.
{"title":"Dynamic reliability indices for k-out-of-n multi-state system","authors":"E. Zaitseva, V. Levashenko, K. Matiaško, S. Puuronen","doi":"10.1109/ISMVL.2005.16","DOIUrl":"https://doi.org/10.1109/ISMVL.2005.16","url":null,"abstract":"A multi-state system k-out-of-n is one of basic models in reliability analysis. In this system, k is the minimum number of n components that must work for the system to work and both the system and its components can have more than two states. A structure function declares relation between system and component states uniquely. New algorithm for reliability analysis of the k-out-of-n multi-state system is proposed in this paper. We use two tools for examine this system: (a) structure function for the system description; (b) direct partial logic derivatives for analysis this system. New algorithm for reliability analysis of the multi-state system k-out-of-n is allowed to calculate the probability of influence i-th system component on the system breakdown or its repairing and the probability of a modification of multi-state system reliability at a change one of the system component states.","PeriodicalId":340578,"journal":{"name":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","volume":"520 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132559844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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