S. Druen, M. Streibl, K. Esmark, K. Domanski, J. Niemesheim, H. Gossner, D. Schmitt-Landsiedel
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引用次数: 1
Abstract
A multi-terminal TLP measurement technique is used for accessing current and voltage distributions during ESD in typical I/O cell frames in a 0.13 um CMOS technology. The procedure extends traditional I/O library testchip based ESD verification and qualification tests, allows to calibrate ESD chip-level simulation tools and to derive precise I/O library application rules.
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