Performance Improvements through Timing Driven Reconfiguration of Black-Boxes in Platform FPGAs

Abstract

Platform FPGAs have introduced complex reconfigurable black-boxes for complete system on chip implementation. With rising expectations from these architectures there is a need to perform optimizations across the FPGA slice fabric and the newly introduced black boxes to maximize performance gains. In this paper, we discuss a timing driven reconfiguration technique to improve performance of DSP designs on platform FPGAs by (i) optimal register placement algorithms within the DSP 48 block and (ii) timing driven mechanism to have maximal pipeline depth.