On reducing wrapper boundary register cells in modular soc testing

Abstract

Motivated by the increasing area and performance overhead caused by wrapping the embedded cores for modular SOC testing, this paper proposes a solution for reducing the number of wrapper boundary register cells. Since the very purpose of core wrappers is to provide controllability and observability for the cores-under-test, it is shown how the number of wrapper boundary register cells can be reduced without affecting the test quality. While a testing time overhead, caused by lower test concurrency, is incurred, there are clear bene$ts in reducing the necessary DFT area and especially in decreasing the propagation delays, which can improve the SOC’s functional timing performance.