{"title":"Dfm - a fabless perspective","authors":"J. Khare","doi":"10.1109/TEST.2003.1271157","DOIUrl":null,"url":null,"abstract":"The fabless model has proven immensely successful for IC companies over the last decade. However, at smaller geometries, process-design interactions are causing design marginality and reliability failures. This paper argues that systematic application of DFM techniques is needed in fabless companies to reduce such (potentially catastrophic} failures. As IC manufacturing technology shifts to 0.13um and below, process-design interactions are becoming very complex. On-chip process variations, pattem-dependent failures, increased via failure rate, etc. are making it harder to separate the process from design using \"simplified\" design rules. In addition, process ramps have become longer, forcing designs into not-so-stable processes. Such a paradigm is new for engineers in fabless companies, who have traditionally been isolated from the process through the interface of design rules and process comers. As a result, an increasing number of SoCs are being designed by fabless companies without understanding the process-design interaction, resulting in","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"51 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Test Conference, 2003. Proceedings. ITC 2003.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TEST.2003.1271157","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The fabless model has proven immensely successful for IC companies over the last decade. However, at smaller geometries, process-design interactions are causing design marginality and reliability failures. This paper argues that systematic application of DFM techniques is needed in fabless companies to reduce such (potentially catastrophic} failures. As IC manufacturing technology shifts to 0.13um and below, process-design interactions are becoming very complex. On-chip process variations, pattem-dependent failures, increased via failure rate, etc. are making it harder to separate the process from design using "simplified" design rules. In addition, process ramps have become longer, forcing designs into not-so-stable processes. Such a paradigm is new for engineers in fabless companies, who have traditionally been isolated from the process through the interface of design rules and process comers. As a result, an increasing number of SoCs are being designed by fabless companies without understanding the process-design interaction, resulting in