Analysis of topologies used for SiC MOSFET circuit modelling

Abstract

At the power converter design stage, the use of simulations is very advantageous provided that the power device model is accurate and enables a fast simulation. To reach these targets, the device model is usually obtained through a divide et impera approach, where each block of the model emulates a specific device characteristic. Such an approach facilitates the development of an accurate model that need low computation effort. The topology used for modelling a Silicon Carbide (SiC) MOSFET can make difficult to reach these targets since the interaction among blocks hinder the aforesaid approach. With this in mind, this paper identifies the problems related to the different topologies proposed by industry and academia. Some solutions are proposed for each type of unwanted interaction that has been detected. Finally, an ideal topology that minimizes interactions is proposed.