{"title":"A compact current steering DAC with component swapping calibration","authors":"U. Nukala, Kye-Shin Lee","doi":"10.1109/DCAS.2010.5955029","DOIUrl":null,"url":null,"abstract":"A compact current steering DAC with component swapping calibration is proposed. By using different reference currents for the upper and lower bits conversion, the number of current sources can be considerably reduced. Therefore, an 8-bit DAC can be realized using only four binary weighted current sources, which reduces the effect of current source mismatch. Furthermore, the performance degradation due to resistor mismatch between the reference current generator and output network is calibrated by swapping the two resistors, and taking the average to obtain the final output of the DAC. As a result, the proposed scheme enables the DAC design using resistors with even poor matching. Circuit level simulation results show the INL is 0.85 LSB with 10% resistor and 1% capacitor mismatch, respectively.","PeriodicalId":405694,"journal":{"name":"2010 IEEE Dallas Circuits and Systems Workshop","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE Dallas Circuits and Systems Workshop","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DCAS.2010.5955029","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
A compact current steering DAC with component swapping calibration is proposed. By using different reference currents for the upper and lower bits conversion, the number of current sources can be considerably reduced. Therefore, an 8-bit DAC can be realized using only four binary weighted current sources, which reduces the effect of current source mismatch. Furthermore, the performance degradation due to resistor mismatch between the reference current generator and output network is calibrated by swapping the two resistors, and taking the average to obtain the final output of the DAC. As a result, the proposed scheme enables the DAC design using resistors with even poor matching. Circuit level simulation results show the INL is 0.85 LSB with 10% resistor and 1% capacitor mismatch, respectively.