Testing of Asynchronous NULL Conventional Logic (NCL) Circuits in Synchronous-Based Desig

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007) Pub Date : 2007-09-26 DOI:10.1109/DFT.2007.40

W. Al-Assadi, S. Kakarla

引用次数: 2

Abstract

Conventional Automatic Test Pattern Generation (ATPG) algorithms would fail when applied to asynchronous circuits due to the absence of a global clock and presence of more state holding elements that synchronize the control and data paths, leading to poor fault coverage. This paper presents a Design for Test (DFT) approach aimed at making asynchronous NCL circuits testable using conventional ATPG tools when incorporated with synchronous-based designs. The proposed approach performs scan and test points insertion on NCL designs using custom ATPG library. Experimental results show significant increase in fault coverage for NCL cyclic and acyclic pipelined designs.

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异步NULL常规逻辑(NCL)电路在同步设计中的测试

传统的自动测试模式生成(ATPG)算法在应用于异步电路时会失败，因为缺乏全局时钟，并且存在更多的状态保持元素来同步控制和数据路径，从而导致较低的故障覆盖率。本文提出了一种测试设计(DFT)方法，旨在使异步NCL电路在与基于同步的设计相结合时使用传统的ATPG工具进行测试。该方法使用自定义ATPG库对NCL设计进行扫描和测试点插入。实验结果表明，NCL循环和非循环管道设计的故障覆盖率显著提高。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)

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