Priyanka Dwivedi, N. Chauhan, Veerendra Dhyani, D. S. Kumar, S. Dhanekar
{"title":"Design, fabrication, characterization and packaging of bottom gate and nano-porous TiO2 based FET","authors":"Priyanka Dwivedi, N. Chauhan, Veerendra Dhyani, D. S. Kumar, S. Dhanekar","doi":"10.1109/NANO.2017.8117298","DOIUrl":null,"url":null,"abstract":"Bottom gate field effect transistors (FETs) with nano-porous TiO2 as channel has been designed, fabricated, characterized and packaged. The fabrication process is simple, scalable and reproducible. Reactive RF sputtering and lift off process was used for depositing and patterning TiO2 respectively. TiO2 was annealed to tune its crystallinity from amorphous to anatase. Microscopy study of TiO2 film reveals nano-porous morphology which improves the surface properties and makes it useful for sensing applications. The transistor characteristics of FET show p-channel behavior and the device has been packaged onto headers for testing it in presence of analytes.","PeriodicalId":292399,"journal":{"name":"2017 IEEE 17th International Conference on Nanotechnology (IEEE-NANO)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE 17th International Conference on Nanotechnology (IEEE-NANO)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NANO.2017.8117298","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
Bottom gate field effect transistors (FETs) with nano-porous TiO2 as channel has been designed, fabricated, characterized and packaged. The fabrication process is simple, scalable and reproducible. Reactive RF sputtering and lift off process was used for depositing and patterning TiO2 respectively. TiO2 was annealed to tune its crystallinity from amorphous to anatase. Microscopy study of TiO2 film reveals nano-porous morphology which improves the surface properties and makes it useful for sensing applications. The transistor characteristics of FET show p-channel behavior and the device has been packaged onto headers for testing it in presence of analytes.
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