T. Sato, S. Mizushima, S. Imai, Y. Suzuki, S. Murata
{"title":"High speed standard cell using bootstrapped technology for LTPSTFT","authors":"T. Sato, S. Mizushima, S. Imai, Y. Suzuki, S. Murata","doi":"10.1109/ISCIT.2007.4392018","DOIUrl":null,"url":null,"abstract":"In this paper, a synchronous high-speed logic standard cells using bootstrapped technology for low temperature poly silicon thin film transistor -liquid crystal display (LTPS TFT-LCD) panel is proposed. The proposed TFT standard cells operate at high frequency region owing to the deep non-saturation operation by using the bootstrapped technology (BST). The proposed TFT standard cells can be reduced the pattern size by using the TFT capacitors for the bootstrapped capacitors. To confirm some characteristics of the proposed TFT standard cells, a full adder (FA) are simulated. As a result, the power delay products obtain about 1/5-9/10 times less value than that of the conventional standard cells using LTPS TFT.","PeriodicalId":331439,"journal":{"name":"2007 International Symposium on Communications and Information Technologies","volume":"42 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 International Symposium on Communications and Information Technologies","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCIT.2007.4392018","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
In this paper, a synchronous high-speed logic standard cells using bootstrapped technology for low temperature poly silicon thin film transistor -liquid crystal display (LTPS TFT-LCD) panel is proposed. The proposed TFT standard cells operate at high frequency region owing to the deep non-saturation operation by using the bootstrapped technology (BST). The proposed TFT standard cells can be reduced the pattern size by using the TFT capacitors for the bootstrapped capacitors. To confirm some characteristics of the proposed TFT standard cells, a full adder (FA) are simulated. As a result, the power delay products obtain about 1/5-9/10 times less value than that of the conventional standard cells using LTPS TFT.