A Low Power Clock Gated Median Filter for Gray Level Images

Abstract

Based on a sorting network, the proposed approximate median filters (APMF) produce acceptable image quality on low-cost hardware. A specialized comparator is being developed to increase the noise-elimination capabilities of such filters. The inexact median filters (IMF) have a regular and modular architecture. Further, to reduce the power consumed by digital systems clock gating is employed. Clock with a View Into the Future Gating is a unique way of computing each FF's clock enabling signals one cycle ahead of time, based on the current cycle data of the FFs it depends on. By allocating a whole clock cycle for the computation of the enabling signals and their propagation, it avoids the strict timing constraints of adaptive geometric features-based filtering (AGFF) and data-driven. In addition, to give a better assessment of intrinsic mode filter (IMF) performance, a novel error evaluation approach based on a histogram-based error dispersion plot was presented. The proposed filter is effective in terms of power, area, and speed, according to simulation findings. The filter's output quality is comparable to that of a precise filter, despite the trade- off between filtering precision and circuit features. In addition, the deterioration is almost unnoticeable to the naked eye. When the clock power is reduced, the entire system's power is reduced as well.