A practical scan re-use scheme for system test

Abstract

This paper presents the work at Texas Instruments for achieving an efficient scan test and IC failure analysis at system level with the advanced scan compression technology. Unlike other approaches that are associated with longer test time, difficult implementation or limited failure analysis capability, the proposed system scan scheme is simply an add-on with ad-hoc scan technologies. The result shows that an ATE-like scan test coverage, including both StuckAt and TFT, was delivered, a more accurate failure diagnostics was achieved.