Multi-step and high-resolution vernier-based TDC architecture

Abstract

A multi-step time-to-digital converter (TDC) architecture, based on a Vernier delay line, that achieves single-cycle latency and high time resolution for high-data-rate applications is presented. The architecture uses multiple TDC stages to reduce the used number of flip-flops and delay elements, which reduces the power consumption. The design details of the two step, three-step TDC architectures have been introduced using the proposed design. A 4-bit TDC has been designed and simulated in 65nm CMOS and compared to a conventional Vernier-based 4-bit TDC circuit. The power consumption is reduced by 50% due to using less circuit components. The design details for a 6-bit TDC that achieves single-cycle latency and high time resolution are also presented.