Addressing EUV patterning challenges towards the limits of NA 0.33 EUV exposure

Abstract

EUV (extreme ultraviolet) lithography is progressively being inserted in high volume manufacturing of semiconductors to keep up with node shrinkage. However, defectivity remains one big challenge to address in order to be able to exploit its full potential. As in any type of lithographic process, processing failures and in-film particles are contributors that need to be reduced by the optimization of coating and development processes and improved dispense systems. On top of these defects, stochastic failures, due to photon shot noise or non-uniformities in the resist, are another major contribution to the defectivity. To support their mitigation, etch process can be used to avoid their transfer to underlying layers. However, it requires a sufficient resist mask thickness. For line and space patterns, providing more resist budget comes with a trade-off which is the increase of pattern collapse failures, especially with shrinking critical dimensions. Collapse mitigation approaches are therefore very important to enable tight pitches and were explored. Stack engineering and especially optimization of resist under layers will be crucial components to enable patterning and defect reduction of shrinking pitches. Finally, as an alternative to traditional chemically amplified resists, metal containing resists are also promising because of their inherent high etch resistance. Dedicated hardware and processes were developed the use of such materials and prevent metal contamination to other tools during further processing steps. In this report will be presented the latest solutions to further decrease defectivity towards manufacturable levels and provide more process margin to achieve better quality patterning towards the limits of NA 0.33 EUV exposure. Furthermore, technologies to improve CD uniformity and stability, which are required for mass production, will also be reported.