Grain boundary barrier height and threshold voltage model of polycrystalline silicon thin film transistors

Abstract

Temperature effect of grain boundary barrier height is simulated considering double exponentials distribution trap states. Two threshold voltage definitions are compared, gate voltage when maximum barrier height occurs and when the condition of equal trapped and free charge interface. And grain size dependence of threshold voltage is also present and compared. Low electric field mobility is computed based on the barrier height model. The results show that barrier height is less dependent on temperature, and more dependent on the trap states density or grain size.