Evolution of a folded floating-gate differential pair

Abstract

The author presents a folded floating-gate MOS (FGMOS) differential pair circuit that is capable of simultaneously providing a rail-to-rail common-mode input voltage range and a rail-to-rail output voltage swing with a low power-supply voltage. In this configuration, the voltage drop across the bias current source is folded up into the same range over which the output voltages swing, facilitating low-voltage operation. The floating-gate charge can be used to trim out the offset voltage of the differential pair and to reduce the required power-supply voltage for a given bias current level. The author provides both a qualitative description of how the circuit works and a quantitative incremental high-frequency analysis of the differential-mode and common-mode transconductance gains and common-mode rejection ratio of the circuit. He also shows experimental measurements from a prototype circuit that was fabricated in a 1.2 /spl mu/m double-poly CMOS process.