A Single-Chip CMOS Transceiver for IEEE 802.11b Wireless LAN

Abstract

A 2.4 G single-chip radio-frequency (RF) transceiver front-end for IEEE 802.11b is integrated in 0.18 mum CMOS technology. The direct conversion architecture is adopted for both transmitter & receiver to minimize the on-chip and off-chip components required, which ensures low cost and low power consumption. The VCO oscillates at two times the carrier frequency to minimize PA pulling effect, which also facilitates the generation of quadrature LOs by using a divide-by-two circuit. It is also promising that further integration of multi-mode transceiver can be facilitated because this architecture maximizes reuse of building blocks in transmitter, receiver and PLL. Primary test results show that the transmit peak error vector magnitude (peak EVM) is less than 16% (rms value about 8.6%) with the spectrum mask requirements met and show that at 4.4 GHz, PLL phase noise is about -119 dBc/Hz at 3 MHz offset.