Using of Bfloat16 Format in Deep Learning Embedded Accelerators based on FPGA with Limited Quantity of Dedicated Multipliers

Abstract

The hardware base of Deep Learning Neural Network (DLNN) realization methods are remote cloud services, Graphical Processing Units (GPU) and Field Programmable Gate Arrays (FPGA). The one of the main differences between FPGA devices is important for DLNN realization is quantity of dedicated multipliers in DSP blocks. In this article a method for optimization based on bfloat16 data format useful for FPGA devices with small quantities of DSP blocks is described.