{"title":"FPGA implementation of an emulator for Wireless Sensor Node with Pt100 temperature sensor","authors":"Uzma Quadri, P. Rangaree, G. Asutkar","doi":"10.1109/TENCON.2013.6719037","DOIUrl":null,"url":null,"abstract":"The paper presents a Field Programmable Gate Array based digital logic emulator capable of implementing Boolean functions which forms a platform for the design of higher combinational and sequential logic circuits. A Wireless Sensor Node has also been designed and implemented to exhibit the functionality of the node's transmitter, receiver and main controller before the actual deployment. RTD Pt100 temperature sensor has been used along with ATmega8L as an input to the transmitter. The FPGA implementation of the system and the simulation results of all the modules have been presented in support of the work.","PeriodicalId":425023,"journal":{"name":"2013 IEEE International Conference of IEEE Region 10 (TENCON 2013)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE International Conference of IEEE Region 10 (TENCON 2013)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TENCON.2013.6719037","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
The paper presents a Field Programmable Gate Array based digital logic emulator capable of implementing Boolean functions which forms a platform for the design of higher combinational and sequential logic circuits. A Wireless Sensor Node has also been designed and implemented to exhibit the functionality of the node's transmitter, receiver and main controller before the actual deployment. RTD Pt100 temperature sensor has been used along with ATmega8L as an input to the transmitter. The FPGA implementation of the system and the simulation results of all the modules have been presented in support of the work.