SoC Development and Prototype with VDK

Abstract

Our team has been developing a System on a Chip (SoC) and is using Synopsys VDK to accelerate both software development and hardware verification. We will discuss how VDK has helped us achieve our primary goal of starting software development and testing prior to design fabrication and our secondary goal of testing our RTL with software. The platform creation process and our transition from RTL-only to Transaction-Level-with-RTL co-simulations will be briefly discussed to provide background. We will also compare our efforts prototyping our design on FPGAs to our experience using VDK. The integration of VDK with an RTL simulator has provided a good balance of simulation speed and visibility down into the design and our engineers have been able to run design validation testing (DVT) software on a large portion of our final RTL prior to our tape out.