SCR-based ESD protection for high bandwidth DRAMs

Abstract

A modified SCR (silicon controlled rectifier) is proposed as an ESD protection for high speed signaling systems. With low voltage triggering (LVT) characteristics and good turn-on uniformity, the proposed SCR scheme accomplishes both goals, high discharging capability and Cin (input capacitance) reduction. The fabricated chips with the new ESD scheme passed the severe package level EOS test conditions such as HBM-5 kV and MM-500 V stress. The input capacitance, Cin, was measured to be 1.5 pF which satisfies the DDR3-1066 specification with enough margin. We have observed in SPICE simulation that the data eye can be enlarged to 277 ps (55.3% of UI) in DDR3 interface at 2 Gbps operation due to the Cin reduction effect.