U. Killat, W. Kowalk, J. Noll, H. Keller, H. J. Fleumerman, U. Ziegler
{"title":"A versatile ATM switch concept","authors":"U. Killat, W. Kowalk, J. Noll, H. Keller, H. J. Fleumerman, U. Ziegler","doi":"10.1109/ISS.1990.770119","DOIUrl":null,"url":null,"abstract":"This contribution deals with a concept for the realization of network nodes in an ATM network. The concept is based on a module called 'M/I -stage', which is derivedfinom the concept of an output buffered switching matrm The M/I -stage is equipped with crosspoint buffers and one output buffer. Taking into account the wiring area of the multiplexed data stream and the area spent for the crosspoint buffers a solution has been developed which minimizes the total chip area of the 'M/I-stage'. Design and implementation of an 8/1-stage as a single IC has been started. Based on this component the architecture of a prototype network node is described.","PeriodicalId":277204,"journal":{"name":"International Symposium on Switching","volume":"15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Symposium on Switching","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISS.1990.770119","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 12
Abstract
This contribution deals with a concept for the realization of network nodes in an ATM network. The concept is based on a module called 'M/I -stage', which is derivedfinom the concept of an output buffered switching matrm The M/I -stage is equipped with crosspoint buffers and one output buffer. Taking into account the wiring area of the multiplexed data stream and the area spent for the crosspoint buffers a solution has been developed which minimizes the total chip area of the 'M/I-stage'. Design and implementation of an 8/1-stage as a single IC has been started. Based on this component the architecture of a prototype network node is described.
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