Split-gate architecture for higher breakdown voltage in STI based LDMOS transistors

Abstract

Conventional Extended gate STI based LDMOS devices often have an overlap between gate and STI resulting in higher impact ionization at the STI left edge. In this work, we have proposed and analyzed a novel split gate architecture to reduce impact ionization and improve off-state breakdown voltage. The underlying physics behind the improved characteristics of the proposed architecture is explained using detailed TCAD simulations. Finally, necessary design guidelines are provided for proper optimization of the split gate architecture.