Pullpipelining: a technique for systolic pipelined circuits

Abstract

Pullpipelining, a pipeline technique where data is pulled from successor stages from predecessor stages is proposed. Control circuits using a synchronous, a semisynchronous and an asynchronous approach are given. Simulation examples for a DLX generic RISC datapath show that common control pipeline circuit overhead is avoided using the proposal. Applications to linear systolic arrays in cases when computation is finished at early stages in the array are foreseen. This would allow run-time data-driven digital frequency modulation of synchronous pipelined designs. This has applications to implement algorithms exhibiting average-case processing time using a synchronous approach.