Column-selection-enabled 8T SRAM array with ∼1R/1W multi-port operation for DVFS-enabled processors

Abstract

In this work, we propose a new multi-port 8T SRAM architecture suitable for DVFS enabled processors. With multi-way caches using 8T SRAM, write-back operations are required to support column selection. While conventional write-back schemes may not have the 1R/1W dual port advantage of 8T SRAM, our proposed local write-back scheme preserves both ports with only minimal limitations. Simulation results show significant IPC enhancements with the proposed cache. Implementation in 45nm technology demonstrates wide-range DVFS (from 120MHZ@0.48V to 710MHz@1V) for the proposed SRAM array.