Pub Date : 2011-08-22DOI: 10.1109/ISLPED.2011.5993610
Yiran Chen, W. Wong, Hai Helen Li, Cheng-Kok Koh
It has been predicted that a processor's caches could occupy as much as 90% of chip area for technology nodes from the current. In this paper, we study the use of multi-level spin-transfer torque RAM (STT-RAM) cells in the design of processor caches. Compared to the traditional SRAM caches, a multi-level cell (MLC) STT-RAM cache design is denser, fast, and consumes less energy. However, a number of critical issues remains to be solved before MLC STT-RAM technology can be deployed in processor caches. In this paper, we shall offer solutions to the issue of bit encoding as well as tackle the write endurance problem. The latter has been neglected in previous works on STT-RAM caches. We propose a set remapping scheme that can potentially prolong the lifetime of a MLC STT-RAM cache by 80× on average. Furthermore, a method for recovering the performance that may be lost in some applications due to set remapping is introduced.
{"title":"Processor caches built using multi-level spin-transfer torque RAM cells","authors":"Yiran Chen, W. Wong, Hai Helen Li, Cheng-Kok Koh","doi":"10.1109/ISLPED.2011.5993610","DOIUrl":"https://doi.org/10.1109/ISLPED.2011.5993610","url":null,"abstract":"It has been predicted that a processor's caches could occupy as much as 90% of chip area for technology nodes from the current. In this paper, we study the use of multi-level spin-transfer torque RAM (STT-RAM) cells in the design of processor caches. Compared to the traditional SRAM caches, a multi-level cell (MLC) STT-RAM cache design is denser, fast, and consumes less energy. However, a number of critical issues remains to be solved before MLC STT-RAM technology can be deployed in processor caches. In this paper, we shall offer solutions to the issue of bit encoding as well as tackle the write endurance problem. The latter has been neglected in previous works on STT-RAM caches. We propose a set remapping scheme that can potentially prolong the lifetime of a MLC STT-RAM cache by 80× on average. Furthermore, a method for recovering the performance that may be lost in some applications due to set remapping is introduced.","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"163 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121263542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-08-01DOI: 10.1109/ISLPED.2011.5993667
K. Takeuchi
SSDs and emerging storage class non-volatile semiconductor memories such as PCRAM, FeRAM, RRAM and MRAM have enabled innovations in various nano-scale VLSI memory systems for personal computers, multimedia applications and enterprise servers [1,2]. This paper provides a comprehensive review on various state-of-the-art memory system architectures and related memory circuits for the green high performance computing.
{"title":"Green high performance storage class memory & NAND flash memory hybrid SSD system","authors":"K. Takeuchi","doi":"10.1109/ISLPED.2011.5993667","DOIUrl":"https://doi.org/10.1109/ISLPED.2011.5993667","url":null,"abstract":"SSDs and emerging storage class non-volatile semiconductor memories such as PCRAM, FeRAM, RRAM and MRAM have enabled innovations in various nano-scale VLSI memory systems for personal computers, multimedia applications and enterprise servers [1,2]. This paper provides a comprehensive review on various state-of-the-art memory system architectures and related memory circuits for the green high performance computing.","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123136178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-08-01DOI: 10.1109/ISLPED.2011.5993613
Woojoo Lee, Younghyun Kim, Yanzhi Wang, N. Chang, Massoud Pedram, Soohee Han
Photovoltaic (PV) cells are promising endurable renewable power sources that do not include mechanical components, which are subject to wear and tear. However, actual development of a solar-powered system requires elaborated design processes to find the best setup including location determination and development of a maximum power point tracking method, which requires numerous on-site experiments. This paper introduces a versatile PV module emulation system, which can cover a range of different PV modules and environmental conditions. We provide an accurate parameter characterization methodology with nonlinear curve fitting to minimize the model discrepancy over the entire operating range. The proposed PV module emulation system includes a pilot PV cell, temperature sensors, an accelerometer, and a magnetic sensor, and provides features for the PV module characterization and emulation modes. Experimental results show significant improvement in the emulation accuracy, which comes from the advanced PV module characterization method as well as high-precision hardware and control.
{"title":"Versatile high-fidelity photovoltaic module emulation system","authors":"Woojoo Lee, Younghyun Kim, Yanzhi Wang, N. Chang, Massoud Pedram, Soohee Han","doi":"10.1109/ISLPED.2011.5993613","DOIUrl":"https://doi.org/10.1109/ISLPED.2011.5993613","url":null,"abstract":"Photovoltaic (PV) cells are promising endurable renewable power sources that do not include mechanical components, which are subject to wear and tear. However, actual development of a solar-powered system requires elaborated design processes to find the best setup including location determination and development of a maximum power point tracking method, which requires numerous on-site experiments. This paper introduces a versatile PV module emulation system, which can cover a range of different PV modules and environmental conditions. We provide an accurate parameter characterization methodology with nonlinear curve fitting to minimize the model discrepancy over the entire operating range. The proposed PV module emulation system includes a pilot PV cell, temperature sensors, an accelerometer, and a magnetic sensor, and provides features for the PV module characterization and emulation modes. Experimental results show significant improvement in the emulation accuracy, which comes from the advanced PV module characterization method as well as high-precision hardware and control.","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129692326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-08-01DOI: 10.1109/ISLPED.2011.5993657
R. Ayoub, Ümit Y. Ogras, E. Gorbatov, Yanqin Jin, T. Kam, Paul Diefenbaugh, T. Simunic
We propose a new DVFS algorithm for enterprise systems that elevates performance as a first order control parameter and manages frequency and voltage as a function of performance requirements. We implement our algorithm on real Intel Westmere platform in Linux and demonstrate its ability to reduce the standard deviation from target performance by more than 90% over state of the art policies while reducing average power by 17%.
{"title":"OS-level power minimization under tight performance constraints in general purpose systems","authors":"R. Ayoub, Ümit Y. Ogras, E. Gorbatov, Yanqin Jin, T. Kam, Paul Diefenbaugh, T. Simunic","doi":"10.1109/ISLPED.2011.5993657","DOIUrl":"https://doi.org/10.1109/ISLPED.2011.5993657","url":null,"abstract":"We propose a new DVFS algorithm for enterprise systems that elevates performance as a first order control parameter and manages frequency and voltage as a function of performance requirements. We implement our algorithm on real Intel Westmere platform in Linux and demonstrate its ability to reduce the standard deviation from target performance by more than 90% over state of the art policies while reducing average power by 17%.","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124377271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-08-01DOI: 10.1109/ISLPED.2011.5993645
Youngtaek Kim, L. John
In this paper, we propose a method for automated di/dt stressmark generation to test maximum voltage droop in a microprocessor power delivery network. The di/dt stressmark is an instruction sequence which draws periodic high and low current pulses that maximize voltage fluctuations including voltage droops. In order to automate di/dt stressmark generation, we devise a code generator with the ability to control instruction sequencing, register assignments, and dependencies. Our framework uses a Genetic Algorithm in scheduling and optimizing candidate instruction sequences to create a maximum voltage droop. The results show that our automatically generated di/dt stressmarks achieved more than 40% average increase in voltage droop compared to hand-coded di/dt stressmarks and typical benchmarks in experiments covering three microprocessor architectures and five power delivery network (PDN) models. Additionally, our method considers all the units in a microprocessor, as opposed to a previous ILP scheduling method that handles only execution units.
{"title":"Automated di/dt stressmark generation for microprocessor power delivery networks","authors":"Youngtaek Kim, L. John","doi":"10.1109/ISLPED.2011.5993645","DOIUrl":"https://doi.org/10.1109/ISLPED.2011.5993645","url":null,"abstract":"In this paper, we propose a method for automated di/dt stressmark generation to test maximum voltage droop in a microprocessor power delivery network. The di/dt stressmark is an instruction sequence which draws periodic high and low current pulses that maximize voltage fluctuations including voltage droops. In order to automate di/dt stressmark generation, we devise a code generator with the ability to control instruction sequencing, register assignments, and dependencies. Our framework uses a Genetic Algorithm in scheduling and optimizing candidate instruction sequences to create a maximum voltage droop. The results show that our automatically generated di/dt stressmarks achieved more than 40% average increase in voltage droop compared to hand-coded di/dt stressmarks and typical benchmarks in experiments covering three microprocessor architectures and five power delivery network (PDN) models. Additionally, our method considers all the units in a microprocessor, as opposed to a previous ILP scheduling method that handles only execution units.","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115795081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-08-01DOI: 10.1109/ISLPED.2011.5993630
H. Fuketa, K. Hirairi, T. Yasufuku, M. Takamiya, M. Nomura, H. Shinohara, T. Sakurai
Contention-less flip-flops (CLFF's) and separated power supply voltages (VDD) between flip-flops (FF's) and combinational logics are proposed to achieve a maximum energy efficiency operation. The proposed technologies were applied to a 16-bit integer unit (IU) for media processing in a 65-nm CMOS process. Measurement results of fabricated chips show that the proposed CLFF reduces the minimum operating voltage of IU's by 64mV on average. By scaling VDD from 1.2V to 310mV with the proposed CLFF, the maximum energy efficiency of 1835GOPS/W and the highest energy efficiency increase of 12.7 times are achieved.
{"title":"12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (VDD) scaling from 1.2V to 310mV enabled by contention-less flip-flops (CLFF) and separated VDD between flip-flops and combinational logics","authors":"H. Fuketa, K. Hirairi, T. Yasufuku, M. Takamiya, M. Nomura, H. Shinohara, T. Sakurai","doi":"10.1109/ISLPED.2011.5993630","DOIUrl":"https://doi.org/10.1109/ISLPED.2011.5993630","url":null,"abstract":"Contention-less flip-flops (CLFF's) and separated power supply voltages (VDD) between flip-flops (FF's) and combinational logics are proposed to achieve a maximum energy efficiency operation. The proposed technologies were applied to a 16-bit integer unit (IU) for media processing in a 65-nm CMOS process. Measurement results of fabricated chips show that the proposed CLFF reduces the minimum operating voltage of IU's by 64mV on average. By scaling VDD from 1.2V to 310mV with the proposed CLFF, the maximum energy efficiency of 1835GOPS/W and the highest energy efficiency increase of 12.7 times are achieved.","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130204618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-08-01DOI: 10.1109/ISLPED.2011.5993640
Ce Li, Yiping Dong, Takahiro Watanabe
The power consumption of FPGA is larger than that of ASIC to perform the same function in the same scaling. In this paper, we propose a Power Control Hard Macro (PCHM) based coarse-grained power gating FPGA architecture to dynamically reduce the power consumption. The algorithm of the placement based on sleep region is presented. After enhancing the CAD framework, a detailed study is given under different region size supported by the new FPGA architecture. As a result, the proposed architecture and the placement algorithm can reduce 51% power consumption on average compared with normal architecture.
{"title":"New power-aware placement for region-based FPGA architecture combined with dynamic power gating by PCHM","authors":"Ce Li, Yiping Dong, Takahiro Watanabe","doi":"10.1109/ISLPED.2011.5993640","DOIUrl":"https://doi.org/10.1109/ISLPED.2011.5993640","url":null,"abstract":"The power consumption of FPGA is larger than that of ASIC to perform the same function in the same scaling. In this paper, we propose a Power Control Hard Macro (PCHM) based coarse-grained power gating FPGA architecture to dynamically reduce the power consumption. The algorithm of the placement based on sleep region is presented. After enhancing the CAD framework, a detailed study is given under different region size supported by the new FPGA architecture. As a result, the proposed architecture and the placement algorithm can reduce 51% power consumption on average compared with normal architecture.","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131043900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-08-01DOI: 10.1109/ISLPED.2011.5993622
V. Hu, M. Fan, P. Su, C. Chuang
This work analyzes the power-performance of the emerging Ultra-Thin-Body (UTB) GeOI devices for logic circuit applications. The impacts of temperature and Vdd scaling on the leakage/delay are studied. Compared with the subthreshold leakage dominated SOI devices/circuits, the band-to-band tunneling dominated leakage currents of GeOI devices/circuits show less sensitivity to temperature. At 300°K and comparable delay, GeOI inverter with smaller band-gap shows larger leakage than the SOI inverter at Vdd = 1.0V, while exhibits lower leakage than the SOI inverter at Vdd = 0.8V. At 400°K, GeOI inverter shows both lower leakage and lower delay at Vdd = 0.6∼1.0V compared with the SOI counterpart, due to the weaker temperature dependence of band-to-band tunneling leakage compared with subthreshold leakage. Compared with the SOI Two-Way NAND and NOR, the GeOI Two-Way NAND and NOR show smaller leakage currents at Vdd = 0.5V or 400°K as the band-to-band tunneling leakage is less sensitive to temperature compared with the subthreshold leakage. Compared with the GeOI domino gate at 400°K, the SOI domino gate shows 5 times degradation in the worst-case noise (dynamic node voltage droop) and 1.4 times increase in the worst-case delay. The GeOI latch leakages are smaller than the SOI counterparts at 300°K (Vdd < 0.8V) and 400°K (Vdd = 0.5∼1.0V).
{"title":"Analysis of power-performance for Ultra-Thin-Body GeOI logic circuits","authors":"V. Hu, M. Fan, P. Su, C. Chuang","doi":"10.1109/ISLPED.2011.5993622","DOIUrl":"https://doi.org/10.1109/ISLPED.2011.5993622","url":null,"abstract":"This work analyzes the power-performance of the emerging Ultra-Thin-Body (UTB) GeOI devices for logic circuit applications. The impacts of temperature and Vdd scaling on the leakage/delay are studied. Compared with the subthreshold leakage dominated SOI devices/circuits, the band-to-band tunneling dominated leakage currents of GeOI devices/circuits show less sensitivity to temperature. At 300°K and comparable delay, GeOI inverter with smaller band-gap shows larger leakage than the SOI inverter at Vdd = 1.0V, while exhibits lower leakage than the SOI inverter at Vdd = 0.8V. At 400°K, GeOI inverter shows both lower leakage and lower delay at Vdd = 0.6∼1.0V compared with the SOI counterpart, due to the weaker temperature dependence of band-to-band tunneling leakage compared with subthreshold leakage. Compared with the SOI Two-Way NAND and NOR, the GeOI Two-Way NAND and NOR show smaller leakage currents at Vdd = 0.5V or 400°K as the band-to-band tunneling leakage is less sensitive to temperature compared with the subthreshold leakage. Compared with the GeOI domino gate at 400°K, the SOI domino gate shows 5 times degradation in the worst-case noise (dynamic node voltage droop) and 1.4 times increase in the worst-case delay. The GeOI latch leakages are smaller than the SOI counterparts at 300°K (Vdd < 0.8V) and 400°K (Vdd = 0.5∼1.0V).","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114744325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-08-01DOI: 10.1109/ISLPED.2011.5993634
A. Zjajo, J. P. D. Gyvez
This paper reports design, optimization, efficiency and measurement results of the 12 bits dual-residue multi-step A/D converter. The calibration procedure based on the steepest-descent estimation method is enhanced with dedicated embedded sensors, which register on-chip process parameter and temperature variations. The prototype A/D converter with performance of 68.6 dB SNDR, 70.3 dB SNR, 78.1 dB SFDR, 11.1 ENOB at 60 MS/s has been fabricated in standard single poly, six metal 90 nm CMOS, consumes only 55 mW and measures 0.75 mm2. The on-chip calibration logic occupies an area of 0.14 mm2 and consumes 11 mW of power.
本文报道了12位双残差多步A/D转换器的设计、优化、效率和测量结果。在基于最陡下降估计法的校准过程中，采用了专用的嵌入式传感器，该传感器可以记录芯片上的工艺参数和温度变化。原型A/D转换器在60 MS/s下具有68.6 dB SNDR、70.3 dB SNR、78.1 dB SFDR和11.1 ENOB的性能，其功耗仅为55 mW，尺寸为0.75 mm2。片上校准逻辑占地0.14 mm2，功耗11 mW。
{"title":"A 1.2V 55mW 12bits self-calibrated dual-residue analog to digital converter in 90 nm CMOS","authors":"A. Zjajo, J. P. D. Gyvez","doi":"10.1109/ISLPED.2011.5993634","DOIUrl":"https://doi.org/10.1109/ISLPED.2011.5993634","url":null,"abstract":"This paper reports design, optimization, efficiency and measurement results of the 12 bits dual-residue multi-step A/D converter. The calibration procedure based on the steepest-descent estimation method is enhanced with dedicated embedded sensors, which register on-chip process parameter and temperature variations. The prototype A/D converter with performance of 68.6 dB SNDR, 70.3 dB SNR, 78.1 dB SFDR, 11.1 ENOB at 60 MS/s has been fabricated in standard single poly, six metal 90 nm CMOS, consumes only 55 mW and measures 0.75 mm2. The on-chip calibration logic occupies an area of 0.14 mm2 and consumes 11 mW of power.","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129749746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We have created sensor architecture, data collection and processing techniques for an E-Textile wireless keyboard. We leverage the inherent properties of E-Textiles to produce optimized architecture for energy efficient sensing. Novel techniques such as one where each sensor senses several events (activations of different keys) and each event is sensed by three sensors and flexible interleaved sensing and data processing result in up to a factor of 30 energy reduction over the system where each key is sensed by exactly one sensor. We build the keyboard and test it on multiple subjects.
{"title":"Energy efficient E-Textile based portable keyboard","authors":"Mahsan Rofouei, M. Potkonjak, M. Sarrafzadeh","doi":"10.5555/2016802.2016878","DOIUrl":"https://doi.org/10.5555/2016802.2016878","url":null,"abstract":"We have created sensor architecture, data collection and processing techniques for an E-Textile wireless keyboard. We leverage the inherent properties of E-Textiles to produce optimized architecture for energy efficient sensing. Novel techniques such as one where each sensor senses several events (activations of different keys) and each event is sensed by three sensors and flexible interleaved sensing and data processing result in up to a factor of 30 energy reduction over the system where each key is sensed by exactly one sensor. We build the keyboard and test it on multiple subjects.","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122345502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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