Design issues for a radiation-tolerant digital-to-analog converter in a commercial 2.0-/spl mu/m BiCMOS process

Abstract

This paper introduces a methodology for using standard commercial processes to design analog integrated circuits that can tolerate the adverse effects of ionizing radiation. First, several devices of various types and sizes were exposed to ionizing radiation and characterized under worst-case biasing conditions with dose rates and maximum total doses as stipulated in circuit specifications. Second, a determination was made as to what types of devices and circuit topologies were best suited for a desired application, given worst-case component parameters. Finally, taking into account the circuit specifications and the expected shifts in device performance, the circuit was designed, simulated, fabricated, and tested. This paper focuses on the design example of a radiation-tolerant 6-bit R-2R ladder digital-to-analog converter (DAC) in a commercial 2.0-/spl mu/m BiCMOS process.