A 6-bit, 4 GSa/s ADC fabricated in a GaAs HBT process

Abstract

A GaAs-AlGaAs Heterojunction Bipolar Transistor (HBT) process was developed to meet the speed, gain and yield requirements for Analog to Digital Converters (ADCs). A 6-bit, 4 GSa/s (4 giga-samples per second) ADC was designed and fabricated in this process. The standard HBT used has an emitter area of 1.4/spl times/3.0 /spl mu/m; it has current gain of over 70 at I/sub c/=1 mA and f/sub T/ and f/sub MAX/ of over 50 GHz at I/sub c/=4 mA. The process also includes Schottky diodes, thin-film NiCr resistors, MIM capacitors and three levels of metal interconnect. The ADC uses an analog folding architecture to reduce transistor count and power well below that of a straight 6-bit flash ADC. It includes an on-chip track-and-hold (T/H) circuit and Gray-encoded digital outputs for best immunity to dynamic errors. The ADC's measured differential nonlinearity is less than /spl plusmn/0.5 LSB and its integral nonlinearity is less than /spl plusmn/0.8 LSB. It has a resolution bandwidth (the frequency at which effective bits has dropped by 0.5 bits) of 2.4 GHz at 3 GSa/s and 1.8 GHz at 4 GSa/s, higher than any ADC published to date. The chip operates at up to 6.5 GSa/s, but linearity at that clock rate is much worse.